1 /*
2 * Copyright (c) 2006-2021, YICHIP Development Team
3 * @file yc_rom_api.h
4 * @brief source file for setting rom_api
5 *
6 * Change Logs:
7 * Date Author Version Notes
8 * 2021-06-23 wushengyan V1.0.0 the first version
9 */
10 #ifndef __RV_31XX_H__
11 #define __RV_31XX_H__
12
13 #ifdef __USE_YC_RISC_V__
14
15 #include "type.h"
16
17 #ifdef __cplusplus
18 extern "C" {
19 #endif
20
21 /* IO definitions (access restrictions to peripheral registers) */
22 #ifdef __cplusplus
23 #define __I volatile /*!< Defines 'read only' permissions */
24 #else
25 #define __I volatile const /*!< Defines 'read only' permissions */
26 #endif
27 #define __O volatile /*!< Defines 'write only' permissions */
28 #define __IO volatile /*!< Defines 'read / write' permissions */
29
30 /* following defines should be used for structure members */
31 #define __IM volatile const /*! Defines 'read only' structure member permissions */
32 #define __OM volatile /*! Defines 'write only' structure member permissions */
33 #define __IOM volatile /*! Defines 'read / write' structure member permissions */
34 /*end IO definitions*/
35
36
37 #define __STATIC_INLINE static __inline
38 /*******************************************************************************
39 * Register Abstraction
40 Core Register contain:
41 - Core Register
42 - Core NVIC PLIC
43 - Core SysTick Register
44 ******************************************************************************/
45
46 /******************** RISC-V REG START **************************************/
47 typedef struct
48 {
49 __IO uint32_t RV_PAUSE_EN : 1;
50 __IO uint32_t RV_PAUSE_START : 1;
51 __IO uint32_t RV_DCLK_EN : 1;
52 __IO uint32_t RV_QSORTCLK_EN : 1;
53 __IO uint32_t RV_BINCLK_EN : 1;
54 __IO uint32_t DBG_STEP_EN : 1;
55 __IO uint32_t FPU_STEP_DIS : 1;
56 __IO uint32_t LONGP_STEP_EN : 1;
57 __IO uint32_t RV_CORECLK_EN : 8;
58 __I uint32_t RV_CTRL_RSVD : 16;
59 __IO uint32_t RV_WKUP_SRC_EN : 32;
60 __IO uint32_t RV_PC_RTVEC : 32;
61 __IO uint32_t RV_STACK_ADDR : 32;
62 } RVCtrl_TypeDef;
63
64 typedef struct
65 {
66 __IO uint32_t ICE_CTRL : 16;
67 __IO uint32_t ICE_CMD : 4;
68 __I uint32_t ICE_CTRL_RSVD : 12;
69 __IO uint32_t ICE_BREAK0 : 25;
70 __I uint32_t ICE_BREAK0_RSVD : 7;
71 __IO uint32_t ICE_BREAK1 : 25;
72 __I uint32_t ICE_BREAK1_RSVD : 7;
73 __IO uint32_t ICE_REG_WDATA : 32;
74 __I uint32_t ICE_REG_RDATA : 32;
75 __IO uint32_t TRACE_ADDR : 25;
76 __I uint32_t TRACE_ADDR_RSVD : 7;
77 __I uint32_t TRACE_FIFO_RDATA : 25;
78 __I uint32_t TRACE_FIFO_RDATA_RSVD : 7;
79 __I uint32_t EXE_ADDR : 32;
80 __I uint32_t ICE_STATUS : 8;
81 __I uint32_t ICE_STATUS_RSVD : 24; //RV_CTRL
82 } RVIce_TypeDef;
83
84 typedef struct
85 {
86 __IO uint32_t BIN_CTRL_BLOCK_ENABLE : 1;
87 __IO uint32_t BIN_CTRL_GRID_MODE : 1;
88 __IO uint32_t BIN_CTRL_CUT_ENABLE : 1;
89 __IO uint32_t BIN_CTRL_SCALER_ENABLE : 1;
90 __IO uint32_t BIN_CTRL_INV_BIT_ENABLE : 1;
91 __I uint32_t BIN_CTRL_RSVD : 3;
92 __IO uint32_t RANGE : 8;
93 __IO uint32_t SUB_HEIGHT : 8;
94 __IO uint32_t SUB_WIDTH : 8;
95
96 __IO uint32_t RAW_BIN_BASEADDR : 24;
97 __I uint32_t RAW_BIN_BASEADDR_RSVD : 8;
98 __IO uint32_t RGB_BASEADDR : 24;
99 __I uint32_t RGB_BASEADDR_RSVD : 8;
100 __IO uint32_t AVG_BASEADDR : 24;
101 __I uint32_t AVG_BASEADDR_RSVD : 8;
102 __IO uint32_t SCA_BIN_BASEADDR : 24;
103 __I uint32_t SCA_BIN_BASEADDR_RSVD : 8;
104
105 __I uint32_t BIN_STATUS : 32;
106 __I uint32_t RAW_DOUT_ADDR_LOCK : 24;
107 __I uint32_t RAW_DOUT_ADDR_LOCK_RSVD : 8;
108 __I uint32_t SCA_DOUT_ADDR_LOCK : 24;
109 __I uint32_t SCA_DOUT_ADDR_LOCK_RSVD : 8;
110 __IO uint32_t QSORT_CTRL : 32;
111 __IO uint32_t QSORT_BASEADDR : 24;
112 __I uint32_t QSORT_BASEADDR_RSVD : 8;
113 __I uint32_t QSORT_DONE : 1;
114 __I uint32_t QSORT_DONE_RSVD : 31;
115
116 __IO uint32_t ONE_RGB_BASEADDR : 24;
117 __I uint32_t ONE_RGB_BASEADDR_RSVD : 8;
118 __IO uint32_t FAST_BIN_BASEADDR : 24;
119 __I uint32_t FAST_BIN_BASEADDR_RSVD : 8;
120 __IO uint32_t CANNY_BIN_BASEADDR : 24;
121 __I uint32_t CANNY_BIN_BASEADDR_RSVD : 8;
122 __IO uint32_t ONE_BIN_CTRL : 13;
123 __I uint32_t ONE_BIN_CTRL_RSVD : 19;
124 __IO uint32_t FAST_BIN_CTRL : 24;
125 __I uint32_t FAST_BIN_CTRL_RSVD : 8;
126 __IO uint32_t CANNY_BIN_CTRL : 23;
127 __I uint32_t CANNY_BIN_CTRL_RSVD : 9;
128 __IO uint32_t CANNY_BIN_CTRL1 : 12;
129 __I uint32_t CANNY_BIN_CTRL1_RSVD : 20;
130 __IO uint32_t ONE_BIN_STATUS : 21;
131 __I uint32_t ONE_BIN_STATUS_RSVD : 11;
132 __IO uint32_t FAST_BIN_BASEADDR_USED : 24;
133 __I uint32_t FAST_BIN_BASEADDR_USED_RSVD : 8;
134 __IO uint32_t CANNY_BIN_BASEADDR_USED : 24;
135 __I uint32_t CANNY_BIN_BASEADDR_USED_RSVD : 8;
136 } RVBin_TypeDef;
137
138 typedef struct
139 {
140 __IO uint32_t JTAG_SW_SEL :1;
141 __I uint32_t JTAG_SW_SEL_RSVD :3;
142 __IO uint32_t DAP_REG_BASE_ADDR :4;
143 __I uint32_t DAP_CTRL_RSVD :24;
144 __IO uint32_t RV_TM_EN :1;
145 __IO uint32_t RV_TM_EN_RSVD :31;
146 __IO uint32_t RV_TM_CNT :32;
147 __IO uint32_t M0_TO_RV_IE :1;
148 __I uint32_t M0_TO_RV_IE_RSVD :7;
149 __IO uint32_t M0_TO_RV_IRQ :1;
150 __I uint32_t M0_TO_RV_IRQ_RSVD :7;
151 __IO uint32_t RV_TO_M0_IRQ_TRIG :1;
152 __I uint32_t RV_TO_M0_IRQ_TRIG_RSVD :15;
153 __IO uint32_t IRQ_SW_EN :1;
154 __IO uint32_t IRQ_SW_PEND :1;
155 __I uint32_t IRQ_SW_RSVD :6;
156 __IO uint32_t IRQ_SW_CODE :8;
157 __I uint32_t RV_SW_IRQ_RSVD :16;
158 }RVIrq_TypeDef;
159
160 #define MPU_REGION_NUM 4
161 typedef struct
162 {
163 __IO uint8_t Protect_region[MPU_REGION_NUM];
164
165 } RVMPUREGION_TypeDef;
166
167 typedef struct
168 {
169 __IO uint32_t BaseAndLimit[MPU_REGION_NUM];
170
171 } RVMPUBASE_TypeDef;
172
173 #define BASE_LIMIT_REGION_NUM 4
174 typedef struct
175 {
176 __IO uint32_t MPU_ENABLE_CODE : 4;
177 __IO RVMPUREGION_TypeDef ICB_PROTECT;
178 __IO RVMPUREGION_TypeDef DTCM_PROTECT;
179 __IO RVMPUREGION_TypeDef ITCM_PROTECT;
180 __IO uint32_t USER_START : 24;
181 __IO uint32_t MPU_STS_CLR;
182 __I uint32_t FAULT_STATUS;
183 __I uint32_t FAULT_ADDR_ICB;
184 __I uint32_t FAULT_ADDR_DTCM;
185 __I uint32_t FAULT_ADDR_ITCM;
186 __IO RVMPUBASE_TypeDef ICB_BASE;
187 __IO RVMPUBASE_TypeDef DTCM_BASE;
188 __IO RVMPUBASE_TypeDef ITCM_BASE;
189 __IO RVMPUBASE_TypeDef ICB_LIMIT;
190 __IO RVMPUBASE_TypeDef DTCM_LIMIT;
191 __IO RVMPUBASE_TypeDef ITCM_LIMIT;
192 } RVMPU_TypeDef;
193
194 typedef struct
195 {
196 __IO uint32_t WDT_EN : 1;
197 __IO uint32_t WDT_EN_LOCK : 1;
198 __IO uint32_t WDT_ACT : 1;
199 __I uint32_t WDT_CTRL_RSVD1 : 5;
200 __IO uint32_t WDT_DIV : 4;
201 __I uint32_t WDT_CTRL_RSVD2 : 20;
202 __IO uint32_t WDT_KEY : 16;
203 __I uint32_t WDT_KEY_RSVD : 16;
204 __IO uint32_t WDT_RELOAD_VALUE : 32;
205 __I uint32_t WDT_CNT : 32;
206 __IO uint32_t WDT_IRQ_EN : 1;
207 __I uint32_t WDT_IRQ_EN_RSVD : 31;
208 __IO uint32_t WDT_IRQ : 1;
209 __I uint32_t WDT_IRQ_RSVD : 31;
210 } RVWdt_TypeDef;
211
212 #define YC3122_RV_BASE (0x000E0000UL) /* RV Base Address */
213
214 #define RV_CTRL_BASEADDR (YC3122_RV_BASE + 0x00000) //0xe0000
215 #define RV_ICE_BASEADDR (YC3122_RV_BASE + 0x00004) //0xe0004
216 #define RV_BIN_BASEADDR (YC3122_RV_BASE + 0x00034) //0xe0034
217 #define RV_IRQ_BASEADDR (YC3122_RV_BASE + 0x000D0) //0xe00d0
218 #define RV_SYSTICK_BASEADDR (YC3122_RV_BASE + 0x000D0) //0xe00d4
219 #define RV_MPU_BASEADDR (YC3122_RV_BASE + 0x00100) //0xe0100
220 #define RV_IRQ_PRIO_BASEADDR (YC3122_RV_BASE + 0x01000) //0xe1000
221 #define RV_IRQ_PEND_BASEADDR (YC3122_RV_BASE + 0x02000) //0xe2000
222 #define RV_IRQ_ENAB_BASEADDR (YC3122_RV_BASE + 0x03000) //0xe3000
223 #define RV_IRQ_THRD_BASEADDR (YC3122_RV_BASE + 0x04000) //0xe4000
224 #define RV_IRQ_CLAM_BASEADDR (YC3122_RV_BASE + 0x04004) //0xe4004
225 #define RV_WDT_BASEADDR (0xfb700) //0xfb700
226
227 #define RV_CTRL1 ((RVCtrl_TypeDef *)RV_CTRL_BASEADDR)
228 #define RV_ICE ((RVIce_TypeDef *)RV_ICE_BASEADDR)
229 #define RV_BIN ((RVBin_TypeDef *)RV_BIN_BASEADDR)
230 #define RISC_IRQ ((RVIrq_TypeDef *)RV_IRQ_BASEADDR)
231
232 /*risc-v mpu map start*/
233 #define RV_MPU_ICB_PROTECT_BASE (RV_MPU_BASEADDR + 0x0004)
234 #define RV_MPU_DTCM_PROTECT_BASE (RV_MPU_ICB_PROTECT_BASE + 0x0004)
235 #define RV_MPU_ITCM_PROTECT_BASE (RV_MPU_DTCM_PROTECT_BASE + 0x0004)
236
237 #define RV_MPU_ICB_BASE_BASE (RV_MPU_BASEADDR + 0x0040)
238 #define RV_MPU_DTCM_BASE_BASE (RV_MPU_ICB_BASE_BASE + 0x0010)
239 #define RV_MPU_ITCM_BASE_BASE (RV_MPU_DTCM_BASE_BASE + 0x0010)
240
241 #define RV_MPU_ICB_LIMIT_BASE (RV_MPU_BASEADDR + 0x0080)
242 #define RV_MPU_DTCM_LIMIT_BASE (RV_MPU_ICB_LIMIT_BASE + 0x0010)
243 #define RV_MPU_ITCM_LIMIT_BASE (RV_MPU_DTCM_LIMIT_BASE + 0x0010)
244
245 /*risc-v mpu reg start*/
246 #define RVMPU ((RVMPU_TypeDef *)RV_MPU_BASEADDR)
247 #define ICB_PROTECTION ((RVMPUREGION_TypeDef *)RV_MPU_ICB_PROTECT_BASE)
248 #define DTCM_PROTECTION ((RVMPUREGION_TypeDef *)RV_MPU_DTCM_PROTECT_BASE)
249 #define ITCM_PROTECTION ((RVMPUREGION_TypeDef *)RV_MPU_ITCM_PROTECT_BASE)
250
251 #define ICB_BASE ((RVMPUBASE_TypeDef *)RV_MPU_ICB_BASE_BASE)
252 #define DTCM_BASE ((RVMPUBASE_TypeDef *)RV_MPU_DTCM_BASE_BASE)
253 #define ITCM_BASE ((RVMPUBASE_TypeDef *)RV_MPU_ITCM_BASE_BASE)
254
255 #define ICB_LIMIT ((RVMPUBASE_TypeDef *)RV_MPU_ICB_LIMIT_BASE)
256 #define DTCM_LIMIT ((RVMPUBASE_TypeDef *)RV_MPU_DTCM_LIMIT_BASE)
257 #define ITCM_LIMIT ((RVMPUBASE_TypeDef *)RV_MPU_ITCM_LIMIT_BASE)
258
259
260 #define RV_WDT ((RVWdt_TypeDef *)RV_WDT_BASEADDR)
261
262 #define RV_IRQ_PRIO(x) *(volatile uint8_t*)(RV_IRQ_PRIO_BASEADDR + ((uint8_t)((uint8_t)(x)/2)))
263 #define RV_IRQ_PEND(x) *(volatile uint8_t*)(RV_IRQ_PEND_BASEADDR + ((uint8_t)((uint8_t)(x)/8)))
264 #define RV_IRQ_ENAB(x) *(volatile uint8_t*)(RV_IRQ_ENAB_BASEADDR + ((uint8_t)((uint8_t)(x)/8)))
265 #define RV_IRQ_THOD *(volatile int*)(RV_IRQ_THRD_BASEADDR)
266 #define RV_IRQ_CLAM *(volatile int*)(RV_IRQ_CLAM_BASEADDR)
267 /******************** RISC-V REG END **************************************/
268
269
270 /**
271 \brief Structure type to access the System Timer (SysTick).
272 */
273 typedef struct
274 {
275 uint32_t TM_EN; /*!< Offset: 0x000 (R/W) SysTick Enable */
276 uint32_t TM_CNT; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
277 } SysTick_Type;
278
279
280
281 #define SysTick ((SysTick_Type *) RV_SYSTICK_BASEADDR ) /*!< SysTick configuration struct */
282 /******************************************************************************/
283
284
285 /**
286 * @method RV EnableIRQ
287 * @brief Enable IRQ
288 * @param IRQn : USB_IRQn...
289 * @retval NULL
290 */
RV_EnableIRQ(IRQn_Type IRQn)291 __STATIC_INLINE void RV_EnableIRQ(IRQn_Type IRQn)
292 {
293 if ((int32_t)(IRQn) >= 0)
294 {
295 RV_IRQ_ENAB(IRQn) |= (uint32_t)(1UL << (uint8_t)((uint8_t)(IRQn)%8));
296 }
297 }
298
299 /**
300 * @method RV DisableIRQ
301 * @brief Disable IRQ
302 * @param IRQn : USB_IRQn...
303 * @retval NULL
304 */
RV_DisableIRQ(IRQn_Type IRQn)305 __STATIC_INLINE void RV_DisableIRQ(IRQn_Type IRQn)
306 {
307 if ((int32_t)(IRQn) >= 0)
308 {
309 RV_IRQ_ENAB(IRQn) &= ~(uint32_t)(1UL << (uint8_t)((uint8_t)(IRQn)%8));
310 }
311 }
312
313 /**
314 * @method RV SetPriority
315 * @brief SetPriority IRQ
316 * @param IRQn : USB_IRQn...
317 * @param priority : 0~15
318 * @retval NULL
319 */
RV_SetPriority(IRQn_Type IRQn,uint32_t priority)320 __STATIC_INLINE void RV_SetPriority(IRQn_Type IRQn, uint32_t priority)
321 {
322 if ((int32_t)(IRQn) >= 0 && priority > 0 && priority < 16)
323 {
324 RV_IRQ_PRIO(IRQn) |= (priority << (uint8_t)((uint8_t)(IRQn)%2)*4);
325 }
326 }
327
328 /**
329 * @method RV Get Pending Interrupt
330 * @brief Reads The PLIC pending register returns the pending bit
331 * @param IRQn : USB_IRQn...
332 * @retval 0: Interrupt status is not pending.
333 * 1: Interrupt status is pending
334 */
RV_GetPendingIRQ(IRQn_Type IRQn)335 __STATIC_INLINE uint32_t RV_GetPendingIRQ(IRQn_Type IRQn)
336 {
337
338 }
339
340 /**
341 * @method RV Get Interrupt Priority
342 * @brief Reads the priority of a device specific interrupt
343 * @param IRQn : USB_IRQn...
344 * @retval Interrupt Priority.
345 */
RV_GetPriority(IRQn_Type IRQn)346 __STATIC_INLINE uint32_t RV_GetPriority(IRQn_Type IRQn)
347 {
348
349 }
350
351 /**
352 * @method NVIC_Configuration
353 * @brief NVIC initialization function for risc-v.
354 * @param IRQn: Interrupt vector numbers could be 0~31.
355 * @param priority: Interrupt priority numbers could be 1~15.
356 * @param newstate: enable or disable
357 * @retval None
358 */
NVIC_Configuration(IRQn_Type IRQn,uint32_t priority,FunctionalState newstate)359 __STATIC_INLINE void NVIC_Configuration(IRQn_Type IRQn, uint32_t priority,FunctionalState newstate)
360 {
361 if(newstate == ENABLE )
362 {
363 RV_EnableIRQ(IRQn);
364 RV_SetPriority(IRQn, priority);
365 }
366 else
367 {
368 RV_DisableIRQ(IRQn);
369 RV_SetPriority(IRQn, priority);
370 }
371 }
372
373 /**
374 * @method SysTick_Config
375 * @brief Initializes the System Timer and its interrupt (priority default 1)
376 * @param ticks: Number of ticks between two interrupts. (0~0xffffffff)
377 * @retval 0: FuncTion succeeded.
378 * 1: Function failed.
379 */
SysTick_Config(uint32_t ticks)380 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
381 {
382 SysTick->TM_CNT = ticks;
383 RV_EnableIRQ(34); /*set systick priority*/
384 RV_SetPriority(34,15);
385 SysTick->TM_EN = 1;
386
387 return (0UL);
388 }
389
390 /**
391 * @method __enable_irq
392 * @brief Enable IRQ Interrupts
393 * @retval NONE.
394 */
__enable_irq(void)395 __STATIC_INLINE void __enable_irq(void)
396 {
397 __asm("csrs mstatus,0x00000008");
398 }
399
400 /**
401 * @method __disable_irq
402 * @brief Disable IRQ Interrupts
403 * @retval NONE.
404 */
__disable_irq(void)405 __STATIC_INLINE void __disable_irq(void)
406 {
407 __asm("csrc mstatus,0x00000008");
408 }
409
410 /*make M0 and RV IRQ equ*/
411 #define NVIC_EnableIRQ RV_EnableIRQ
412 #define NVIC_DisableIRQ RV_DisableIRQ
413 #define NVIC_SetPriority RV_SetPriority
414 #define NVIC_GetPendingIRQ RV_GetPendingIRQ
415 /*end*/
416
417
418 #ifdef __cplusplus
419 }
420 #endif
421
422 #endif
423 #endif
424