1 /****************************************************************************** 2 * Copyright (C) 2013 - 2020 Xilinx, Inc. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 ******************************************************************************/ 5 6 /*****************************************************************************/ 7 /** 8 * 9 * @file xsdps.h 10 * @addtogroup sdps_v3_9 11 * @{ 12 * @details 13 * 14 * This file contains the implementation of XSdPs driver. 15 * This driver is used initialize read from and write to the SD card. 16 * Features such as switching bus width to 4-bit and switching to high speed, 17 * changing clock frequency, block size etc. are supported. 18 * SD 2.0 uses 1/4 bus width and speeds of 25/50KHz. Initialization, however 19 * is done using 1-bit bus width and 400KHz clock frequency. 20 * SD commands are classified as broadcast and addressed. Commands can be 21 * those with response only (using only command line) or 22 * response + data (using command and data lines). 23 * Only one command can be sent at a time. During a data transfer however, 24 * when dsta lines are in use, certain commands (which use only the command 25 * line) can be sent, most often to obtain status. 26 * This driver does not support multi card slots at present. 27 * 28 * Initialization: 29 * This includes initialization on the host controller side to select 30 * clock frequency, bus power and default transfer related parameters. 31 * The default voltage is 3.3V. 32 * On the SD card side, the initialization and identification state diagram is 33 * implemented. This resets the card, gives it a unique address/ID and 34 * identifies key card related specifications. 35 * 36 * Data transfer: 37 * The SD card is put in transfer state to read from or write to it. 38 * The default block size is 512 bytes and if supported, 39 * default bus width is 4-bit and bus speed is High speed. 40 * The read and write functions are implemented in polled mode using ADMA2. 41 * 42 * At any point, when key parameters such as block size or 43 * clock/speed or bus width are modified, this driver takes care of 44 * maintaining the same selection on host and card. 45 * All error bits in host controller are monitored by the driver and in the 46 * event one of them is set, driver will clear the interrupt status and 47 * communicate failure to the upper layer. 48 * 49 * File system use: 50 * This driver can be used with xilffs library to read and write files to SD. 51 * (Please refer to procedure in diskio.c). The file system read/write example 52 * in polled mode can used for reference. 53 * 54 * There is no example for using SD driver without file system at present. 55 * However, the driver can be used without the file system. The glue layer 56 * in filesystem can be used as reference for the same. The block count 57 * passed to the read/write function in one call is limited by the ADMA2 58 * descriptor table and hence care will have to be taken to call read/write 59 * API's in a loop for large file sizes. 60 * 61 * Interrupt mode is not supported because it offers no improvement when used 62 * with file system. 63 * 64 * eMMC support: 65 * SD driver supports SD and eMMC based on the "enable MMC" parameter in SDK. 66 * The features of eMMC supported by the driver will depend on those supported 67 * by the host controller. The current driver supports read/write on eMMC card 68 * using 4-bit and high speed mode currently. 69 * 70 * Features not supported include - card write protect, password setting, 71 * lock/unlock, interrupts, SDMA mode, programmed I/O mode and 72 * 64-bit addressed ADMA2, erase/pre-erase commands. 73 * 74 * <pre> 75 * MODIFICATION HISTORY: 76 * 77 * Ver Who Date Changes 78 * ----- --- -------- ----------------------------------------------- 79 * 1.00a hk/sg 10/17/13 Initial release 80 * 2.0 hk 03/07/14 Version number revised. 81 * 2.1 hk 04/18/14 Increase sleep for eMMC switch command. 82 * Add sleep for microblaze designs. CR# 781117. 83 * 2.2 hk 07/28/14 Make changes to enable use of data cache. 84 * 2.3 sk 09/23/14 Send command for relative card address 85 * when re-initialization is done.CR# 819614. 86 * Use XSdPs_Change_ClkFreq API whenever changing 87 * clock.CR# 816586. 88 * 2.4 sk 12/04/14 Added support for micro SD without 89 * WP/CD. CR# 810655. 90 * Checked for DAT Inhibit mask instead of CMD 91 * Inhibit mask in Cmd Transfer API. 92 * Added Support for SD Card v1.0 93 * 2.5 sg 07/09/15 Added SD 3.0 features 94 * kvn 07/15/15 Modified the code according to MISRAC-2012. 95 * 2.6 sk 10/12/15 Added support for SD card v1.0 CR# 840601. 96 * 2.7 sk 11/24/15 Considered the slot type befoe checking CD/WP pins. 97 * sk 12/10/15 Added support for MMC cards. 98 * 01/08/16 Added workaround for issue in auto tuning mode 99 * of SDR50, SDR104 and HS200. 100 * sk 02/16/16 Corrected the Tuning logic. 101 * sk 03/01/16 Removed Bus Width check for eMMC. CR# 938311. 102 * 2.8 sk 04/20/16 Added new workaround for auto tuning. 103 * 05/03/16 Standard Speed for SD to 19MHz in ZynqMPSoC. CR#951024 104 * 3.0 sk 06/09/16 Added support for mkfs to calculate sector count. 105 * sk 07/16/16 Added support for UHS modes. 106 * sk 07/07/16 Used usleep API for both arm and microblaze. 107 * sk 07/16/16 Added Tap delays accordingly to different SD/eMMC 108 * operating modes. 109 * sk 08/13/16 Removed sleep.h from xsdps.h as a temporary fix for 110 * CR#956899. 111 * 3.1 mi 09/07/16 Removed compilation warnings with extra compiler flags. 112 * sk 10/13/16 Reduced the delay during power cycle to 1ms as per spec 113 * sk 10/19/16 Used emmc_hwreset pin to reset eMMC. 114 * sk 11/07/16 Enable Rst_n bit in ext_csd reg if not enabled. 115 * sk 11/16/16 Issue DLL reset at 31 iteration to load new zero value. 116 * 3.2 sk 11/30/16 Modified the voltage switching sequence as per spec. 117 * sk 02/01/17 Added HSD and DDR mode support for eMMC. 118 * sk 02/01/17 Consider bus width parameter from design for switching 119 * vns 02/09/17 Added ARMA53_32 support for ZynqMP CR#968397 120 * sk 03/20/17 Add support for EL1 non-secure mode. 121 * 3.3 mn 05/17/17 Add support for 64bit DMA addressing 122 * mn 08/07/17 Modify driver to support 64-bit DMA in arm64 only 123 * mn 08/17/17 Enabled CCI support for A53 by adding cache coherency 124 * information. 125 * mn 09/06/17 Resolved compilation errors with IAR toolchain 126 * 3.6 mn 08/01/18 Add support for using 64Bit DMA with 32-Bit Processor 127 * 3.7 mn 02/01/19 Add support for idling of SDIO 128 * 3.8 mn 04/12/19 Modified TapDelay code for supporting ZynqMP and Versal 129 * mn 09/17/19 Modified ADMA handling API for 32bit and 64bit addresses 130 * 3.9 mn 03/03/20 Restructured the code for more readability and modularity 131 * mn 03/16/20 Move XSdPs_Select_Card API to User APIs 132 * 133 * </pre> 134 * 135 ******************************************************************************/ 136 137 138 #ifndef SDPS_H_ 139 #define SDPS_H_ 140 141 #ifdef __cplusplus 142 extern "C" { 143 #endif 144 145 #include "xil_printf.h" 146 #include "xil_cache.h" 147 #include "xstatus.h" 148 #include "xsdps_hw.h" 149 #include "xplatform_info.h" 150 #include "sleep.h" 151 #include <string.h> 152 #if defined (XCLOCKING) 153 #include "xil_clocking.h" 154 #endif 155 156 /************************** Constant Definitions *****************************/ 157 158 #define XSDPS_CT_ERROR 0x2L /**< Command timeout flag */ 159 #define MAX_TUNING_COUNT 40U /**< Maximum Tuning count */ 160 #define MAX_TIMEOUT 0x1FFFFFFFU /**< Maximum Timeout */ 161 #define XSDPS_CMD8_VOL_PATTERN 0x1AAU 162 #define XSDPS_RESPOCR_READY 0x80000000U 163 #define XSDPS_ACMD41_HCS 0x40000000U 164 #define XSDPS_ACMD41_3V3 0x00300000U 165 #define XSDPS_CMD1_HIGH_VOL 0x00FF8000U 166 #define XSDPS_CMD1_DUAL_VOL 0x00FF8010U 167 #define HIGH_SPEED_SUPPORT 0x2U 168 #define UHS_SDR12_SUPPORT 0x1U 169 #define UHS_SDR25_SUPPORT 0x2U 170 #define UHS_SDR50_SUPPORT 0x4U 171 #define UHS_SDR104_SUPPORT 0x8U 172 #define UHS_DDR50_SUPPORT 0x10U 173 #define WIDTH_4_BIT_SUPPORT 0x4U 174 #define SD_CLK_25_MHZ 25000000U 175 #define SD_CLK_19_MHZ 19000000U 176 #define SD_CLK_26_MHZ 26000000U 177 #define EXT_CSD_DEVICE_TYPE_BYTE 196U 178 #define EXT_CSD_SEC_COUNT_BYTE1 212U 179 #define EXT_CSD_SEC_COUNT_BYTE2 213U 180 #define EXT_CSD_SEC_COUNT_BYTE3 214U 181 #define EXT_CSD_SEC_COUNT_BYTE4 215U 182 #define EXT_CSD_DEVICE_TYPE_HIGH_SPEED 0x2U 183 #define EXT_CSD_DEVICE_TYPE_DDR_1V8_HIGH_SPEED 0x4U 184 #define EXT_CSD_DEVICE_TYPE_DDR_1V2_HIGH_SPEED 0x8U 185 #define EXT_CSD_DEVICE_TYPE_SDR_1V8_HS200 0x10U 186 #define EXT_CSD_DEVICE_TYPE_SDR_1V2_HS200 0x20U 187 #define CSD_SPEC_VER_3 0x3U 188 #define SCR_SPEC_VER_3 0x80U 189 #define ADDRESS_BEYOND_32BIT 0x100000000U 190 191 /**************************** Type Definitions *******************************/ 192 193 typedef void (*XSdPs_ConfigTap) (u32 Bank, u32 DeviceId, u32 CardType); 194 195 /** 196 * This typedef contains configuration information for the device. 197 */ 198 typedef struct { 199 u16 DeviceId; /**< Unique ID of device */ 200 u32 BaseAddress; /**< Base address of the device */ 201 u32 InputClockHz; /**< Input clock frequency */ 202 u32 CardDetect; /**< Card Detect */ 203 u32 WriteProtect; /**< Write Protect */ 204 u32 BusWidth; /**< Bus Width */ 205 u32 BankNumber; /**< MIO Bank selection for SD */ 206 u32 HasEMIO; /**< If SD is connected to EMIO */ 207 u8 IsCacheCoherent; /**< If SD is Cache Coherent or not */ 208 #if defined (XCLOCKING) 209 u32 RefClk; /**< Input clocks */ 210 #endif 211 } XSdPs_Config; 212 213 /* ADMA2 32-Bit descriptor table */ 214 typedef struct { 215 u16 Attribute; /**< Attributes of descriptor */ 216 u16 Length; /**< Length of current dma transfer */ 217 u32 Address; /**< Address of current dma transfer */ 218 #ifdef __ICCARM__ 219 #pragma data_alignment = 32 220 } XSdPs_Adma2Descriptor32; 221 #else 222 } __attribute__((__packed__))XSdPs_Adma2Descriptor32; 223 #endif 224 225 /* ADMA2 64-Bit descriptor table */ 226 typedef struct { 227 u16 Attribute; /**< Attributes of descriptor */ 228 u16 Length; /**< Length of current dma transfer */ 229 u64 Address; /**< Address of current dma transfer */ 230 #ifdef __ICCARM__ 231 #pragma data_alignment = 32 232 } XSdPs_Adma2Descriptor64; 233 #else 234 } __attribute__((__packed__))XSdPs_Adma2Descriptor64; 235 #endif 236 237 /** 238 * The XSdPs driver instance data. The user is required to allocate a 239 * variable of this type for every SD device in the system. A pointer 240 * to a variable of this type is then passed to the driver API functions. 241 */ 242 typedef struct { 243 XSdPs_Config Config; /**< Configuration structure */ 244 u32 IsReady; /**< Device is initialized and ready */ 245 u32 Host_Caps; /**< Capabilities of host controller */ 246 u32 Host_CapsExt; /**< Extended Capabilities */ 247 u32 HCS; /**< High capacity support in card */ 248 u8 CardType; /**< Type of card - SD/MMC/eMMC */ 249 u8 Card_Version; /**< Card version */ 250 u8 HC_Version; /**< Host controller version */ 251 u8 BusWidth; /**< Current operating bus width */ 252 u32 BusSpeed; /**< Current operating bus speed */ 253 u8 Switch1v8; /**< 1.8V Switch support */ 254 u32 CardID[4]; /**< Card ID Register */ 255 u32 RelCardAddr; /**< Relative Card Address */ 256 u32 CardSpecData[4]; /**< Card Specific Data Register */ 257 u32 SectorCount; /**< Sector Count */ 258 u32 SdCardConfig; /**< Sd Card Configuration Register */ 259 u32 Mode; /**< Bus Speed Mode */ 260 u32 OTapDelay; /**< Output Tap Delay */ 261 u32 ITapDelay; /**< Input Tap Delay */ 262 u64 Dma64BitAddr; /**< 64 Bit DMA Address */ 263 u16 TransferMode; /**< Transfer Mode */ 264 u32 SlcrBaseAddr; /**< SLCR base address*/ 265 } XSdPs; 266 267 /***************** Macros (Inline Functions) Definitions *********************/ 268 269 /************************** Function Prototypes ******************************/ 270 XSdPs_Config *XSdPs_LookupConfig(u16 DeviceId); 271 s32 XSdPs_CfgInitialize(XSdPs *InstancePtr, XSdPs_Config *ConfigPtr, 272 u32 EffectiveAddr); 273 s32 XSdPs_CardInitialize(XSdPs *InstancePtr); 274 s32 XSdPs_ReadPolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, u8 *Buff); 275 s32 XSdPs_WritePolled(XSdPs *InstancePtr, u32 Arg, u32 BlkCnt, const u8 *Buff); 276 s32 XSdPs_Idle(XSdPs *InstancePtr); 277 278 s32 XSdPs_Change_BusSpeed(XSdPs *InstancePtr); 279 s32 XSdPs_Change_ClkFreq(XSdPs *InstancePtr, u32 SelFreq); 280 s32 XSdPs_Pullup(XSdPs *InstancePtr); 281 s32 XSdPs_Get_BusWidth(XSdPs *InstancePtr, u8 *ReadBuff); 282 s32 XSdPs_Change_BusWidth(XSdPs *InstancePtr); 283 s32 XSdPs_Get_BusSpeed(XSdPs *InstancePtr, u8 *ReadBuff); 284 s32 XSdPs_Get_Mmc_ExtCsd(XSdPs *InstancePtr, u8 *ReadBuff); 285 s32 XSdPs_Set_Mmc_ExtCsd(XSdPs *InstancePtr, u32 Arg); 286 s32 XSdPs_SetBlkSize(XSdPs *InstancePtr, u16 BlkSize); 287 s32 XSdPs_Get_Status(XSdPs *InstancePtr, u8 *SdStatReg); 288 s32 XSdPs_Select_Card(XSdPs *InstancePtr); 289 290 #ifdef __cplusplus 291 } 292 #endif 293 294 #endif /* SD_H_ */ 295 /** @} */ 296