1 /****************************************************************************** 2 * Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved. 3 * SPDX-License-Identifier: MIT 4 ******************************************************************************/ 5 6 /*****************************************************************************/ 7 /** 8 * @file xparameters_ps.h 9 * 10 * @addtogroup r5_peripheral_definitions Cortex R5 peripheral definitions 11 * 12 * The xparameters_ps.h file contains the canonical definitions and constant 13 * declarations for peripherals within hardblock, attached to the ARM Cortex R5 14 * core. These definitions can be used by drivers or applications to access the 15 * peripherals. 16 * 17 * @{ 18 * <pre> 19 * MODIFICATION HISTORY: 20 * 21 * Ver Who Date Changes 22 * ----- ------- -------- --------------------------------------------------- 23 * 5.00 pkp 02/29/14 Initial version 24 * 6.0 mus 08/18/16 Defined ARMR5 flag 25 * 7.2 pm 03/25/20 Add wakeup Interrupt Id for usbpsu controller 26 * </pre> 27 * 28 ******************************************************************************/ 29 30 #ifndef XPARAMETERS_PS_H_ 31 #define XPARAMETERS_PS_H_ 32 33 #ifndef ARMR5 34 #define ARMR5 ARMR5 35 #endif 36 37 #ifdef __cplusplus 38 extern "C" { 39 #endif 40 41 /***************************** Include Files *********************************/ 42 43 /************************** Constant Definitions *****************************/ 44 45 /* 46 * This block contains constant declarations for the peripherals 47 * within the hardblock 48 */ 49 50 /* Canonical definitions for DDR MEMORY */ 51 #define XPAR_DDR_MEM_BASEADDR 0x00000000U 52 #define XPAR_DDR_MEM_HIGHADDR 0x3FFFFFFFU 53 54 /* Canonical definitions for Interrupts */ 55 #define XPAR_XUARTPS_0_INTR XPS_UART0_INT_ID 56 #define XPAR_XUARTPS_1_INTR XPS_UART1_INT_ID 57 #define XPAR_XIICPS_0_INTR XPS_I2C0_INT_ID 58 #define XPAR_XIICPS_1_INTR XPS_I2C1_INT_ID 59 #define XPAR_XSPIPS_0_INTR XPS_SPI0_INT_ID 60 #define XPAR_XSPIPS_1_INTR XPS_SPI1_INT_ID 61 #define XPAR_XCANPS_0_INTR XPS_CAN0_INT_ID 62 #define XPAR_XCANPS_1_INTR XPS_CAN1_INT_ID 63 #define XPAR_XGPIOPS_0_INTR XPS_GPIO_INT_ID 64 #define XPAR_XEMACPS_0_INTR XPS_GEM0_INT_ID 65 #define XPAR_XEMACPS_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID 66 #define XPAR_XEMACPS_1_INTR XPS_GEM1_INT_ID 67 #define XPAR_XEMACPS_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID 68 #define XPAR_XEMACPS_2_INTR XPS_GEM2_INT_ID 69 #define XPAR_XEMACPS_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID 70 #define XPAR_XEMACPS_3_INTR XPS_GEM3_INT_ID 71 #define XPAR_XEMACPS_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID 72 #define XPAR_XSDIOPS_0_INTR XPS_SDIO0_INT_ID 73 #define XPAR_XQSPIPS_0_INTR XPS_QSPI_INT_ID 74 #define XPAR_XSDIOPS_1_INTR XPS_SDIO1_INT_ID 75 #define XPAR_XWDTPS_0_INTR XPS_CSU_WDT_INT_ID 76 #define XPAR_XWDTPS_1_INTR XPS_LPD_SWDT_INT_ID 77 #define XPAR_XWDTPS_2_INTR XPS_FPD_SWDT_INT_ID 78 #define XPAR_XDCFG_0_INTR XPS_DVC_INT_ID 79 #define XPAR_XTTCPS_0_INTR XPS_TTC0_0_INT_ID 80 #define XPAR_XTTCPS_1_INTR XPS_TTC0_1_INT_ID 81 #define XPAR_XTTCPS_2_INTR XPS_TTC0_2_INT_ID 82 #define XPAR_XTTCPS_3_INTR XPS_TTC1_0_INT_ID 83 #define XPAR_XTTCPS_4_INTR XPS_TTC1_1_INT_ID 84 #define XPAR_XTTCPS_5_INTR XPS_TTC1_2_INT_ID 85 #define XPAR_XTTCPS_6_INTR XPS_TTC2_0_INT_ID 86 #define XPAR_XTTCPS_7_INTR XPS_TTC2_1_INT_ID 87 #define XPAR_XTTCPS_8_INTR XPS_TTC2_2_INT_ID 88 #define XPAR_XTTCPS_9_INTR XPS_TTC3_0_INT_ID 89 #define XPAR_XTTCPS_10_INTR XPS_TTC3_1_INT_ID 90 #define XPAR_XTTCPS_11_INTR XPS_TTC3_2_INT_ID 91 #define XPAR_XNANDPS8_0_INTR XPS_NAND_INT_ID 92 #define XPAR_XADMAPS_0_INTR XPS_ADMA_CH0_INT_ID 93 #define XPAR_XADMAPS_1_INTR XPS_ADMA_CH1_INT_ID 94 #define XPAR_XADMAPS_2_INTR XPS_ADMA_CH2_INT_ID 95 #define XPAR_XADMAPS_3_INTR XPS_ADMA_CH3_INT_ID 96 #define XPAR_XADMAPS_4_INTR XPS_ADMA_CH4_INT_ID 97 #define XPAR_XADMAPS_5_INTR XPS_ADMA_CH5_INT_ID 98 #define XPAR_XADMAPS_6_INTR XPS_ADMA_CH6_INT_ID 99 #define XPAR_XADMAPS_7_INTR XPS_ADMA_CH7_INT_ID 100 #define XPAR_XCSUDMA_INTR XPS_CSU_DMA_INT_ID 101 #define XPAR_PSU_ADMA_0_INTR XPS_ADMA_CH0_INT_ID 102 #define XPAR_PSU_ADMA_1_INTR XPS_ADMA_CH1_INT_ID 103 #define XPAR_PSU_ADMA_2_INTR XPS_ADMA_CH2_INT_ID 104 #define XPAR_PSU_ADMA_3_INTR XPS_ADMA_CH3_INT_ID 105 #define XPAR_PSU_ADMA_4_INTR XPS_ADMA_CH4_INT_ID 106 #define XPAR_PSU_ADMA_5_INTR XPS_ADMA_CH5_INT_ID 107 #define XPAR_PSU_ADMA_6_INTR XPS_ADMA_CH6_INT_ID 108 #define XPAR_PSU_ADMA_7_INTR XPS_ADMA_CH7_INT_ID 109 #define XPAR_PSU_CSUDMA_INTR XPS_CSU_DMA_INT_ID 110 #define XPAR_XMPU_LPD_INTR XPS_XMPU_LPD_INT_ID 111 #define XPAR_XZDMAPS_0_INTR XPS_ZDMA_CH0_INT_ID 112 #define XPAR_XZDMAPS_1_INTR XPS_ZDMA_CH1_INT_ID 113 #define XPAR_XZDMAPS_2_INTR XPS_ZDMA_CH2_INT_ID 114 #define XPAR_XZDMAPS_3_INTR XPS_ZDMA_CH3_INT_ID 115 #define XPAR_XZDMAPS_4_INTR XPS_ZDMA_CH4_INT_ID 116 #define XPAR_XZDMAPS_5_INTR XPS_ZDMA_CH5_INT_ID 117 #define XPAR_XZDMAPS_6_INTR XPS_ZDMA_CH6_INT_ID 118 #define XPAR_XZDMAPS_7_INTR XPS_ZDMA_CH7_INT_ID 119 #define XPAR_PSU_GDMA_0_INTR XPS_ZDMA_CH0_INT_ID 120 #define XPAR_PSU_GDMA_1_INTR XPS_ZDMA_CH1_INT_ID 121 #define XPAR_PSU_GDMA_2_INTR XPS_ZDMA_CH2_INT_ID 122 #define XPAR_PSU_GDMA_3_INTR XPS_ZDMA_CH3_INT_ID 123 #define XPAR_PSU_GDMA_4_INTR XPS_ZDMA_CH4_INT_ID 124 #define XPAR_PSU_GDMA_5_INTR XPS_ZDMA_CH5_INT_ID 125 #define XPAR_PSU_GDMA_6_INTR XPS_ZDMA_CH6_INT_ID 126 #define XPAR_PSU_GDMA_7_INTR XPS_ZDMA_CH7_INT_ID 127 #define XPAR_XMPU_FPD_INTR XPS_XMPU_FPD_INT_ID 128 #define XPAR_XCCI_FPD_INTR XPS_FPD_CCI_INT_ID 129 #define XPAR_XSMMU_FPD_INTR XPS_FPD_SMMU_INT_ID 130 #define XPAR_XUSBPS_0_INTR XPS_USB3_0_ENDPT_INT_ID 131 #define XPAR_XUSBPS_1_INTR XPS_USB3_1_ENDPT_INT_ID 132 #define XPAR_XUSBPS_0_WAKE_INTR XPS_USB3_0_WAKE_INT_ID 133 #define XPAR_XUSBPS_1_WAKE_INTR XPS_USB3_1_WAKE_INT_ID 134 #define XPAR_XRTCPSU_ALARM_INTR XPS_RTC_ALARM_INT_ID 135 #define XPAR_XRTCPSU_SECONDS_INTR XPS_RTC_SEC_INT_ID 136 #define XPAR_XAPMPS_0_INTR XPS_APM0_INT_ID 137 #define XPAR_XAPMPS_1_INTR XPS_APM1_INT_ID 138 #define XPAR_XAPMPS_2_INTR XPS_APM2_INT_ID 139 #define XPAR_XAPMPS_5_INTR XPS_APM5_INT_ID 140 #define XPAR_XSYSMONPSU_INTR XPS_AMS_INT_ID 141 142 /* Canonical definitions for SCU GIC */ 143 #define XPAR_SCUGIC_NUM_INSTANCES 1U 144 #define XPAR_SCUGIC_SINGLE_DEVICE_ID 0U 145 #define XPAR_SCUGIC_CPU_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00001000U) 146 #define XPAR_SCUGIC_DIST_BASEADDR (XPS_SCU_PERIPH_BASE + 0x00002000U) 147 #define XPAR_SCUGIC_ACK_BEFORE 0U 148 149 #define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 150 151 152 /* 153 * This block contains constant declarations for the peripherals 154 * within the hardblock. These have been put for bacwards compatibility 155 */ 156 157 #define XPS_SYS_CTRL_BASEADDR 0xFF180000U 158 #define XPS_SCU_PERIPH_BASE 0xF9000000U 159 160 161 /* Shared Peripheral Interrupts (SPI) */ 162 #define XPS_FPGA0_INT_ID 121U 163 #define XPS_FPGA1_INT_ID 122U 164 #define XPS_FPGA2_INT_ID 123U 165 #define XPS_FPGA3_INT_ID 124U 166 #define XPS_FPGA4_INT_ID 125U 167 #define XPS_FPGA5_INT_ID 126U 168 #define XPS_FPGA6_INT_ID 127U 169 #define XPS_FPGA7_INT_ID 128U 170 #define XPS_FPGA8_INT_ID 136U 171 #define XPS_FPGA9_INT_ID 137U 172 #define XPS_FPGA10_INT_ID 138U 173 #define XPS_FPGA11_INT_ID 139U 174 #define XPS_FPGA12_INT_ID 140U 175 #define XPS_FPGA13_INT_ID 141U 176 #define XPS_FPGA14_INT_ID 142U 177 #define XPS_FPGA15_INT_ID 143U 178 179 /* Updated Interrupt-IDs */ 180 #define XPS_OCMINTR_INT_ID (10U + 32U) 181 #define XPS_NAND_INT_ID (14U + 32U) 182 #define XPS_QSPI_INT_ID (15U + 32U) 183 #define XPS_GPIO_INT_ID (16U + 32U) 184 #define XPS_I2C0_INT_ID (17U + 32U) 185 #define XPS_I2C1_INT_ID (18U + 32U) 186 #define XPS_SPI0_INT_ID (19U + 32U) 187 #define XPS_SPI1_INT_ID (20U + 32U) 188 #define XPS_UART0_INT_ID (21U + 32U) 189 #define XPS_UART1_INT_ID (22U + 32U) 190 #define XPS_CAN0_INT_ID (23U + 32U) 191 #define XPS_CAN1_INT_ID (24U + 32U) 192 #define XPS_RTC_ALARM_INT_ID (26U + 32U) 193 #define XPS_RTC_SEC_INT_ID (27U + 32U) 194 #define XPS_LPD_SWDT_INT_ID (52U + 32U) 195 #define XPS_CSU_WDT_INT_ID (53U + 32U) 196 #define XPS_FPD_SWDT_INT_ID (113U + 32U) 197 #define XPS_TTC0_0_INT_ID (36U + 32U) 198 #define XPS_TTC0_1_INT_ID (37U + 32U) 199 #define XPS_TTC0_2_INT_ID (38U + 32U) 200 #define XPS_TTC1_0_INT_ID (39U + 32U) 201 #define XPS_TTC1_1_INT_ID (40U + 32U) 202 #define XPS_TTC1_2_INT_ID (41U + 32U) 203 #define XPS_TTC2_0_INT_ID (42U + 32U) 204 #define XPS_TTC2_1_INT_ID (43U + 32U) 205 #define XPS_TTC2_2_INT_ID (44U + 32U) 206 #define XPS_TTC3_0_INT_ID (45U + 32U) 207 #define XPS_TTC3_1_INT_ID (46U + 32U) 208 #define XPS_TTC3_2_INT_ID (47U + 32U) 209 #define XPS_SDIO0_INT_ID (48U + 32U) 210 #define XPS_SDIO1_INT_ID (49U + 32U) 211 #define XPS_AMS_INT_ID (56U + 32U) 212 #define XPS_GEM0_INT_ID (57U + 32U) 213 #define XPS_GEM0_WAKE_INT_ID (58U + 32U) 214 #define XPS_GEM1_INT_ID (59U + 32U) 215 #define XPS_GEM1_WAKE_INT_ID (60U + 32U) 216 #define XPS_GEM2_INT_ID (61U + 32U) 217 #define XPS_GEM2_WAKE_INT_ID (62U + 32U) 218 #define XPS_GEM3_INT_ID (63U + 32U) 219 #define XPS_GEM3_WAKE_INT_ID (64U + 32U) 220 #define XPS_USB3_0_ENDPT_INT_ID (65U + 32U) 221 #define XPS_USB3_1_ENDPT_INT_ID (70U + 32U) 222 #define XPS_USB3_0_WAKE_INT_ID (75U + 32U) 223 #define XPS_USB3_1_WAKE_INT_ID (76U + 32U) 224 #define XPS_ADMA_CH0_INT_ID (77U + 32U) 225 #define XPS_ADMA_CH1_INT_ID (78U + 32U) 226 #define XPS_ADMA_CH2_INT_ID (79U + 32U) 227 #define XPS_ADMA_CH3_INT_ID (80U + 32U) 228 #define XPS_ADMA_CH4_INT_ID (81U + 32U) 229 #define XPS_ADMA_CH5_INT_ID (82U + 32U) 230 #define XPS_ADMA_CH6_INT_ID (83U + 32U) 231 #define XPS_ADMA_CH7_INT_ID (84U + 32U) 232 #define XPS_CSU_DMA_INT_ID (86U + 32U) 233 #define XPS_XMPU_LPD_INT_ID (88U + 32U) 234 #define XPS_ZDMA_CH0_INT_ID (124U + 32U) 235 #define XPS_ZDMA_CH1_INT_ID (125U + 32U) 236 #define XPS_ZDMA_CH2_INT_ID (126U + 32U) 237 #define XPS_ZDMA_CH3_INT_ID (127U + 32U) 238 #define XPS_ZDMA_CH4_INT_ID (128U + 32U) 239 #define XPS_ZDMA_CH5_INT_ID (129U + 32U) 240 #define XPS_ZDMA_CH6_INT_ID (130U + 32U) 241 #define XPS_ZDMA_CH7_INT_ID (131U + 32U) 242 #define XPS_XMPU_FPD_INT_ID (134U + 32U) 243 #define XPS_FPD_CCI_INT_ID (154U + 32U) 244 #define XPS_FPD_SMMU_INT_ID (155U + 32U) 245 #define XPS_APM0_INT_ID (123U + 32U) 246 #define XPS_APM1_INT_ID (25U + 32U) 247 #define XPS_APM2_INT_ID (25U + 32U) 248 #define XPS_APM5_INT_ID (123U + 32U) 249 250 /* REDEFINES for TEST APP */ 251 #define XPAR_PSU_UART_0_INTR XPS_UART0_INT_ID 252 #define XPAR_PSU_UART_1_INTR XPS_UART1_INT_ID 253 #define XPAR_PSU_USB_0_INTR XPS_USB0_INT_ID 254 #define XPAR_PSU_USB_1_INTR XPS_USB1_INT_ID 255 #define XPAR_PSU_I2C_0_INTR XPS_I2C0_INT_ID 256 #define XPAR_PSU_I2C_1_INTR XPS_I2C1_INT_ID 257 #define XPAR_PSU_SPI_0_INTR XPS_SPI0_INT_ID 258 #define XPAR_PSU_SPI_1_INTR XPS_SPI1_INT_ID 259 #define XPAR_PSU_CAN_0_INTR XPS_CAN0_INT_ID 260 #define XPAR_PSU_CAN_1_INTR XPS_CAN1_INT_ID 261 #define XPAR_PSU_GPIO_0_INTR XPS_GPIO_INT_ID 262 #define XPAR_PSU_ETHERNET_0_INTR XPS_GEM0_INT_ID 263 #define XPAR_PSU_ETHERNET_0_WAKE_INTR XPS_GEM0_WAKE_INT_ID 264 #define XPAR_PSU_ETHERNET_1_INTR XPS_GEM1_INT_ID 265 #define XPAR_PSU_ETHERNET_1_WAKE_INTR XPS_GEM1_WAKE_INT_ID 266 #define XPAR_PSU_ETHERNET_2_INTR XPS_GEM2_INT_ID 267 #define XPAR_PSU_ETHERNET_2_WAKE_INTR XPS_GEM2_WAKE_INT_ID 268 #define XPAR_PSU_ETHERNET_3_INTR XPS_GEM3_INT_ID 269 #define XPAR_PSU_ETHERNET_3_WAKE_INTR XPS_GEM3_WAKE_INT_ID 270 #define XPAR_PSU_QSPI_0_INTR XPS_QSPI_INT_ID 271 #define XPAR_PSU_WDT_0_INTR XPS_LPD_SWDT_INT_ID 272 #define XPAR_PSU_WDT_1_INTR XPS_FPD_SWDT_INT_ID 273 #define XPAR_PSU_XADC_0_INTR XPS_SYSMON_INT_ID 274 #define XPAR_PSU_TTC_0_INTR XPS_TTC0_0_INT_ID 275 #define XPAR_PSU_TTC_1_INTR XPS_TTC0_1_INT_ID 276 #define XPAR_PSU_TTC_2_INTR XPS_TTC0_2_INT_ID 277 #define XPAR_PSU_TTC_3_INTR XPS_TTC1_0_INT_ID 278 #define XPAR_PSU_TTC_4_INTR XPS_TTC1_1_INT_ID 279 #define XPAR_PSU_TTC_5_INTR XPS_TTC1_2_INT_ID 280 #define XPAR_PSU_TTC_6_INTR XPS_TTC2_0_INT_ID 281 #define XPAR_PSU_TTC_7_INTR XPS_TTC2_1_INT_ID 282 #define XPAR_PSU_TTC_8_INTR XPS_TTC2_2_INT_ID 283 #define XPAR_PSU_TTC_9_INTR XPS_TTC3_0_INT_ID 284 #define XPAR_PSU_TTC_10_INTR XPS_TTC3_1_INT_ID 285 #define XPAR_PSU_TTC_11_INTR XPS_TTC3_2_INT_ID 286 #define XPAR_PSU_AMS_INTR XPS_AMS_INT_ID 287 288 #define XPAR_XADCPS_NUM_INSTANCES 1U 289 #define XPAR_XADCPS_0_DEVICE_ID 0U 290 #define XPAR_XADCPS_0_BASEADDR (0xF8007000U) 291 #define XPAR_XADCPS_INT_ID XPS_SYSMON_INT_ID 292 293 /* For backwards compatibility */ 294 #define XPAR_XUARTPS_0_CLOCK_HZ XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 295 #define XPAR_XUARTPS_1_CLOCK_HZ XPAR_XUARTPS_1_UART_CLK_FREQ_HZ 296 #define XPAR_XTTCPS_0_CLOCK_HZ XPAR_XTTCPS_0_TTC_CLK_FREQ_HZ 297 #define XPAR_XTTCPS_1_CLOCK_HZ XPAR_XTTCPS_1_TTC_CLK_FREQ_HZ 298 #define XPAR_XTTCPS_2_CLOCK_HZ XPAR_XTTCPS_2_TTC_CLK_FREQ_HZ 299 #define XPAR_XTTCPS_3_CLOCK_HZ XPAR_XTTCPS_3_TTC_CLK_FREQ_HZ 300 #define XPAR_XTTCPS_4_CLOCK_HZ XPAR_XTTCPS_4_TTC_CLK_FREQ_HZ 301 #define XPAR_XTTCPS_5_CLOCK_HZ XPAR_XTTCPS_5_TTC_CLK_FREQ_HZ 302 #define XPAR_XIICPS_0_CLOCK_HZ XPAR_XIICPS_0_I2C_CLK_FREQ_HZ 303 #define XPAR_XIICPS_1_CLOCK_HZ XPAR_XIICPS_1_I2C_CLK_FREQ_HZ 304 305 #define XPAR_XQSPIPS_0_CLOCK_HZ XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 306 307 #ifdef XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 308 #define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_0_CPU_CLK_FREQ_HZ 309 #endif 310 311 #ifdef XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ 312 #define XPAR_CPU_CORTEXR5_CORE_CLOCK_FREQ_HZ XPAR_CPU_CORTEXR5_1_CPU_CLK_FREQ_HZ 313 #endif 314 315 #define XPAR_SCUWDT_DEVICE_ID 0U 316 317 318 #ifdef __cplusplus 319 } 320 #endif 321 322 #endif /* protection macro */ 323 /** 324 * @} End of "addtogroup r5_peripheral_definitions". 325 */ 326