1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2020-03-19     WangHuachen  the first version
9  */
10 #include <rthw.h>
11 #include <rtthread.h>
12 #include <stdint.h>
13 
14 #include "drv_timer.h"
15 
16 #define TTC0_0_BASEADDR     XPAR_PSU_TTC_0_BASEADDR
17 #define TTC0_0_CLK_FREQ_HZ  XPAR_PSU_TTC_0_TTC_CLK_FREQ_HZ
18 
19 
rt_hw_timer_isr(int vector,void * param)20 static void rt_hw_timer_isr(int vector, void *param)
21 {
22     rt_tick_increase();
23     /* clear interrupt */
24     TTC_ISR(TTC0_0_BASEADDR);
25 }
26 
rt_hw_timer_init(void)27 static int rt_hw_timer_init(void)
28 {
29     /* Stop timer */
30     TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_DIS_MASK;
31 
32     /* Initialize TTC */
33     TTC_CNT_CNTRL(TTC0_0_BASEADDR) = TTC_CNT_CNTRL_RESET_VALUE;
34     TTC_CLK_CNTRL(TTC0_0_BASEADDR) = 0x00;
35     TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = 0x00;
36     TTC_MATCH_0(TTC0_0_BASEADDR) = 0x00;
37     TTC_MATCH_1(TTC0_0_BASEADDR) = 0x00;
38     TTC_MATCH_2(TTC0_0_BASEADDR) = 0x00;
39     TTC_IER(TTC0_0_BASEADDR) = 0x00;
40     TTC_ISR(TTC0_0_BASEADDR) = 0x00;
41 
42     /* Reset counter */
43     TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_RST_MASK;
44 
45     /* Interval mode select */
46     TTC_CNT_CNTRL(TTC0_0_BASEADDR) |= TTC_CNT_CNTRL_INT_MASK;
47     /* Setup interval */
48     TTC_INTERVAL_VAL(TTC0_0_BASEADDR) = TTC0_0_CLK_FREQ_HZ / RT_TICK_PER_SECOND;
49     /* Clear all of the prescaler control bits in the register */
50     TTC_CLK_CNTRL(TTC0_0_BASEADDR) &= ~(TTC_CLK_CNTRL_PS_VAL_MASK |
51                                             TTC_CLK_CNTRL_PS_EN_MASK);
52     /* We do not need a prescaler*/
53 
54     /* Register the ticker handler with the GIC */
55     rt_hw_interrupt_install(XPAR_XTTCPS_0_INTR, rt_hw_timer_isr, RT_NULL, "tick");
56     /* Enable TTC interrupts in the GIC */
57     rt_hw_interrupt_umask(XPAR_XTTCPS_0_INTR);
58     /* Enable interval interrupt */
59     TTC_IER(TTC0_0_BASEADDR) |= TTC_IXR_INTERVAL_MASK;
60     /* Start timer */
61     TTC_CNT_CNTRL(TTC0_0_BASEADDR) &=~ TTC_CNT_CNTRL_DIS_MASK;
62 
63     return RT_EOK;
64 }
65 INIT_BOARD_EXPORT(rt_hw_timer_init);
66