1 /*
2 * Copyright (c) 2006-2023, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2012-04-25 weety first version
9 */
10
11 #include <rtdevice.h>
12
13 #define DBG_TAG "I2C"
14 #ifdef RT_I2C_BITOPS_DEBUG
15 #define DBG_LVL DBG_LOG
16 #else
17 #define DBG_LVL DBG_INFO
18 #endif
19 #include <rtdbg.h>
20
21 #define SET_SDA(ops, val) ops->set_sda(ops->data, val)
22 #define SET_SCL(ops, val) ops->set_scl(ops->data, val)
23 #define GET_SDA(ops) ops->get_sda(ops->data)
24 #define GET_SCL(ops) ops->get_scl(ops->data)
25
i2c_delay(struct rt_i2c_bit_ops * ops)26 rt_inline void i2c_delay(struct rt_i2c_bit_ops *ops)
27 {
28 ops->udelay((ops->delay_us + 1) >> 1);
29 }
30
i2c_delay2(struct rt_i2c_bit_ops * ops)31 rt_inline void i2c_delay2(struct rt_i2c_bit_ops *ops)
32 {
33 ops->udelay(ops->delay_us);
34 }
35
36 #define SDA_L(ops) SET_SDA(ops, 0)
37 #define SDA_H(ops) SET_SDA(ops, 1)
38 #define SCL_L(ops) SET_SCL(ops, 0)
39
40 /**
41 * release scl line, and wait scl line to high.
42 */
SCL_H(struct rt_i2c_bit_ops * ops)43 static rt_err_t SCL_H(struct rt_i2c_bit_ops *ops)
44 {
45 rt_tick_t start;
46
47 SET_SCL(ops, 1);
48
49 if (!ops->get_scl)
50 goto done;
51
52 start = rt_tick_get();
53 while (!GET_SCL(ops))
54 {
55 if ((rt_tick_get() - start) > ops->timeout)
56 return -RT_ETIMEOUT;
57 i2c_delay(ops);
58 }
59 #ifdef RT_I2C_BITOPS_DEBUG
60 if (rt_tick_get() != start)
61 {
62 LOG_D("wait %ld tick for SCL line to go high",
63 rt_tick_get() - start);
64 }
65 #endif
66
67 done:
68 i2c_delay(ops);
69
70 return RT_EOK;
71 }
72
i2c_start(struct rt_i2c_bit_ops * ops)73 static void i2c_start(struct rt_i2c_bit_ops *ops)
74 {
75 #ifdef RT_I2C_BITOPS_DEBUG
76 if (ops->get_scl && !GET_SCL(ops))
77 {
78 LOG_E("I2C bus error, SCL line low");
79 }
80 if (ops->get_sda && !GET_SDA(ops))
81 {
82 LOG_E("I2C bus error, SDA line low");
83 }
84 #endif
85 SDA_L(ops);
86 i2c_delay(ops);
87 SCL_L(ops);
88 }
89
i2c_restart(struct rt_i2c_bit_ops * ops)90 static void i2c_restart(struct rt_i2c_bit_ops *ops)
91 {
92 SDA_H(ops);
93 SCL_H(ops);
94 i2c_delay(ops);
95 SDA_L(ops);
96 i2c_delay(ops);
97 SCL_L(ops);
98 }
99
i2c_stop(struct rt_i2c_bit_ops * ops)100 static void i2c_stop(struct rt_i2c_bit_ops *ops)
101 {
102 SDA_L(ops);
103 i2c_delay(ops);
104 SCL_H(ops);
105 i2c_delay(ops);
106 SDA_H(ops);
107 i2c_delay2(ops);
108 }
109
i2c_waitack(struct rt_i2c_bit_ops * ops)110 rt_inline rt_bool_t i2c_waitack(struct rt_i2c_bit_ops *ops)
111 {
112 rt_bool_t ack;
113
114 SDA_H(ops);
115 i2c_delay(ops);
116
117 if (SCL_H(ops) < 0)
118 {
119 LOG_W("wait ack timeout");
120
121 return -RT_ETIMEOUT;
122 }
123
124 ack = !GET_SDA(ops); /* ACK : SDA pin is pulled low */
125 LOG_D("%s", ack ? "ACK" : "NACK");
126
127 SCL_L(ops);
128
129 return ack;
130 }
131
i2c_writeb(struct rt_i2c_bus_device * bus,rt_uint8_t data)132 static rt_int32_t i2c_writeb(struct rt_i2c_bus_device *bus, rt_uint8_t data)
133 {
134 rt_int32_t i;
135 rt_uint8_t bit;
136
137 struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
138
139 for (i = 7; i >= 0; i--)
140 {
141 SCL_L(ops);
142 bit = (data >> i) & 1;
143 SET_SDA(ops, bit);
144 i2c_delay(ops);
145 if (SCL_H(ops) < 0)
146 {
147 LOG_D("i2c_writeb: 0x%02x, "
148 "wait scl pin high timeout at bit %d",
149 data, i);
150
151 return -RT_ETIMEOUT;
152 }
153 }
154 SCL_L(ops);
155 i2c_delay(ops);
156
157 return i2c_waitack(ops);
158 }
159
i2c_readb(struct rt_i2c_bus_device * bus)160 static rt_int32_t i2c_readb(struct rt_i2c_bus_device *bus)
161 {
162 rt_uint8_t i;
163 rt_uint8_t data = 0;
164 struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
165
166 SDA_H(ops);
167 i2c_delay(ops);
168 for (i = 0; i < 8; i++)
169 {
170 data <<= 1;
171
172 if (SCL_H(ops) < 0)
173 {
174 LOG_D("i2c_readb: wait scl pin high "
175 "timeout at bit %d", 7 - i);
176
177 return -RT_ETIMEOUT;
178 }
179
180 if (GET_SDA(ops))
181 data |= 1;
182 SCL_L(ops);
183 i2c_delay2(ops);
184 }
185
186 return data;
187 }
188
i2c_send_bytes(struct rt_i2c_bus_device * bus,struct rt_i2c_msg * msg)189 static rt_ssize_t i2c_send_bytes(struct rt_i2c_bus_device *bus,
190 struct rt_i2c_msg *msg)
191 {
192 rt_int32_t ret;
193 rt_size_t bytes = 0;
194 const rt_uint8_t *ptr = msg->buf;
195 rt_int32_t count = msg->len;
196 rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
197
198 while (count > 0)
199 {
200 ret = i2c_writeb(bus, *ptr);
201
202 if ((ret > 0) || (ignore_nack && (ret == 0)))
203 {
204 count --;
205 ptr ++;
206 bytes ++;
207 }
208 else if (ret == 0)
209 {
210 LOG_D("send bytes: NACK.");
211
212 return 0;
213 }
214 else
215 {
216 LOG_E("send bytes: error %d", ret);
217
218 return ret;
219 }
220 }
221
222 return bytes;
223 }
224
i2c_send_ack_or_nack(struct rt_i2c_bus_device * bus,int ack)225 static rt_err_t i2c_send_ack_or_nack(struct rt_i2c_bus_device *bus, int ack)
226 {
227 struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
228
229 if (ack)
230 SET_SDA(ops, 0);
231 i2c_delay(ops);
232 if (SCL_H(ops) < 0)
233 {
234 LOG_E("ACK or NACK timeout.");
235
236 return -RT_ETIMEOUT;
237 }
238 SCL_L(ops);
239
240 return RT_EOK;
241 }
242
i2c_recv_bytes(struct rt_i2c_bus_device * bus,struct rt_i2c_msg * msg)243 static rt_ssize_t i2c_recv_bytes(struct rt_i2c_bus_device *bus,
244 struct rt_i2c_msg *msg)
245 {
246 rt_int32_t val;
247 rt_int32_t bytes = 0; /* actual bytes */
248 rt_uint8_t *ptr = msg->buf;
249 rt_int32_t count = msg->len;
250 const rt_uint32_t flags = msg->flags;
251
252 while (count > 0)
253 {
254 val = i2c_readb(bus);
255 if (val >= 0)
256 {
257 *ptr = val;
258 bytes ++;
259 }
260 else
261 {
262 break;
263 }
264
265 ptr ++;
266 count --;
267
268 LOG_D("recieve bytes: 0x%02x, %s",
269 val, (flags & RT_I2C_NO_READ_ACK) ?
270 "(No ACK/NACK)" : (count ? "ACK" : "NACK"));
271
272 if (!(flags & RT_I2C_NO_READ_ACK))
273 {
274 val = i2c_send_ack_or_nack(bus, count);
275 if (val < 0)
276 return val;
277 }
278 }
279
280 return bytes;
281 }
282
i2c_send_address(struct rt_i2c_bus_device * bus,rt_uint8_t addr,rt_int32_t retries)283 static rt_int32_t i2c_send_address(struct rt_i2c_bus_device *bus,
284 rt_uint8_t addr,
285 rt_int32_t retries)
286 {
287 struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
288 rt_int32_t i;
289 rt_err_t ret = 0;
290
291 for (i = 0; i <= retries; i++)
292 {
293 ret = i2c_writeb(bus, addr);
294 if (ret == 1 || i == retries)
295 break;
296 LOG_D("send stop condition");
297 i2c_stop(ops);
298 i2c_delay2(ops);
299 LOG_D("send start condition");
300 i2c_start(ops);
301 }
302
303 return ret;
304 }
305
i2c_bit_send_address(struct rt_i2c_bus_device * bus,struct rt_i2c_msg * msg)306 static rt_err_t i2c_bit_send_address(struct rt_i2c_bus_device *bus,
307 struct rt_i2c_msg *msg)
308 {
309 rt_uint16_t flags = msg->flags;
310 rt_uint16_t ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
311 struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
312
313 rt_uint8_t addr1, addr2;
314 rt_int32_t retries;
315 rt_err_t ret;
316
317 retries = ignore_nack ? 0 : bus->retries;
318
319 if (flags & RT_I2C_ADDR_10BIT)
320 {
321 addr1 = 0xf0 | ((msg->addr >> 7) & 0x06);
322 addr2 = msg->addr & 0xff;
323
324 LOG_D("addr1: %d, addr2: %d", addr1, addr2);
325
326 ret = i2c_send_address(bus, addr1, retries);
327 if ((ret != 1) && !ignore_nack)
328 {
329 LOG_W("NACK: sending first addr");
330
331 return -RT_EIO;
332 }
333
334 ret = i2c_writeb(bus, addr2);
335 if ((ret != 1) && !ignore_nack)
336 {
337 LOG_W("NACK: sending second addr");
338
339 return -RT_EIO;
340 }
341 if (flags & RT_I2C_RD)
342 {
343 LOG_D("send repeated start condition");
344 i2c_restart(ops);
345 addr1 |= 0x01;
346 ret = i2c_send_address(bus, addr1, retries);
347 if ((ret != 1) && !ignore_nack)
348 {
349 LOG_E("NACK: sending repeated addr");
350
351 return -RT_EIO;
352 }
353 }
354 }
355 else
356 {
357 /* 7-bit addr */
358 addr1 = msg->addr << 1;
359 if (flags & RT_I2C_RD)
360 addr1 |= 1;
361 ret = i2c_send_address(bus, addr1, retries);
362 if ((ret != 1) && !ignore_nack)
363 return -RT_EIO;
364 }
365
366 return RT_EOK;
367 }
368
i2c_bit_xfer(struct rt_i2c_bus_device * bus,struct rt_i2c_msg msgs[],rt_uint32_t num)369 static rt_ssize_t i2c_bit_xfer(struct rt_i2c_bus_device *bus,
370 struct rt_i2c_msg msgs[],
371 rt_uint32_t num)
372 {
373 struct rt_i2c_msg *msg;
374 struct rt_i2c_bit_ops *ops = (struct rt_i2c_bit_ops *)bus->priv;
375 rt_int32_t ret;
376 rt_uint32_t i;
377 rt_uint16_t ignore_nack;
378
379 if((ops->i2c_pin_init_flag == RT_FALSE) && (ops->pin_init != RT_NULL))
380 {
381 ops->pin_init();
382 ops->i2c_pin_init_flag = RT_TRUE;
383 }
384
385 if (num == 0) return 0;
386
387 for (i = 0; i < num; i++)
388 {
389 msg = &msgs[i];
390 ignore_nack = msg->flags & RT_I2C_IGNORE_NACK;
391 if (!(msg->flags & RT_I2C_NO_START))
392 {
393 if (i)
394 {
395 i2c_restart(ops);
396 }
397 else
398 {
399 LOG_D("send start condition");
400 i2c_start(ops);
401 }
402 ret = i2c_bit_send_address(bus, msg);
403 if ((ret != RT_EOK) && !ignore_nack)
404 {
405 LOG_D("receive NACK from device addr 0x%02x msg %d",
406 msgs[i].addr, i);
407 goto out;
408 }
409 }
410 if (msg->flags & RT_I2C_RD)
411 {
412 ret = i2c_recv_bytes(bus, msg);
413 if (ret >= 1)
414 {
415 LOG_D("read %d byte%s", ret, ret == 1 ? "" : "s");
416 }
417 if (ret < msg->len)
418 {
419 if (ret >= 0)
420 ret = -RT_EIO;
421 goto out;
422 }
423 }
424 else
425 {
426 ret = i2c_send_bytes(bus, msg);
427 if (ret >= 1)
428 {
429 LOG_D("write %d byte%s", ret, ret == 1 ? "" : "s");
430 }
431 if (ret < msg->len)
432 {
433 if (ret >= 0)
434 ret = -RT_ERROR;
435 goto out;
436 }
437 }
438 }
439 ret = i;
440
441 out:
442 if (!(msg->flags & RT_I2C_NO_STOP))
443 {
444 LOG_D("send stop condition");
445 i2c_stop(ops);
446 }
447
448 return ret;
449 }
450
451 static const struct rt_i2c_bus_device_ops i2c_bit_bus_ops =
452 {
453 i2c_bit_xfer,
454 RT_NULL,
455 RT_NULL
456 };
457
rt_i2c_bit_add_bus(struct rt_i2c_bus_device * bus,const char * bus_name)458 rt_err_t rt_i2c_bit_add_bus(struct rt_i2c_bus_device *bus,
459 const char *bus_name)
460 {
461 bus->ops = &i2c_bit_bus_ops;
462
463 return rt_i2c_bus_device_register(bus, bus_name);
464 }
465