1 /*
2 * Copyright (c) 2006-2022, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2022-08-25 GuEe-GUI first version
9 */
10
11 #include <rtthread.h>
12
13 #include <drivers/pic.h>
14 #include <drivers/ofw.h>
15 #include <drivers/ofw_io.h>
16 #include <drivers/ofw_irq.h>
17
18 #define DBG_TAG "rtdm.ofw"
19 #define DBG_LVL DBG_INFO
20 #include <rtdbg.h>
21
22 #include "ofw_internal.h"
23
ofw_interrupt_cells(struct rt_ofw_node * np)24 static int ofw_interrupt_cells(struct rt_ofw_node *np)
25 {
26 int interrupt_cells = -RT_EEMPTY;
27
28 rt_ofw_prop_read_u32(np, "#interrupt-cells", (rt_uint32_t *)&interrupt_cells);
29
30 return interrupt_cells;
31 }
32
rt_ofw_irq_cells(struct rt_ofw_node * np)33 int rt_ofw_irq_cells(struct rt_ofw_node *np)
34 {
35 return np ? ofw_interrupt_cells(np) : -RT_EINVAL;
36 }
37
ofw_parse_irq_map(struct rt_ofw_node * np,struct rt_ofw_cell_args * irq_args)38 static rt_err_t ofw_parse_irq_map(struct rt_ofw_node *np, struct rt_ofw_cell_args *irq_args)
39 {
40 rt_err_t err = RT_EOK;
41 rt_phandle ic_phandle = 0;
42 rt_ssize_t map_len, map_mask_len;
43 struct rt_ofw_node *ic_np = RT_NULL;
44 const fdt32_t *addr, *map, *map_mask;
45 int child_address_cells, child_interrupt_cells;
46 int parent_address_cells = 0, parent_interrupt_cells = 0;
47 int addr_cells, pin_cells, icaddr_cells, idx1, idx2, limit;
48
49 /*
50 * interrupt-map:
51 * An interrupt-map is a property on a nexus node that bridges one
52 * interrupt domain with a set of parent interrupt domains and specifies
53 * how interrupt specifiers in the child domain are mapped to
54 * their respective parent domains.
55 *
56 * The interrupt map is a table where each row is a mapping entry
57 * consisting of five components: child unit address, child interrupt
58 * specifier, interrupt-parent, parent unit address, parent interrupt
59 * specifier.
60 *
61 * child unit address
62 * The unit address of the child node being mapped. The number of
63 * 32-bit cells required to specify this is described by the
64 * #address-cells property of the bus node on which the child is
65 * located.
66 *
67 * child interrupt specifier
68 * The interrupt specifier of the child node being mapped. The number
69 * of 32-bit cells required to specify this component is described by
70 * the #interrupt-cells property of this node-the nexus node containing
71 * the interrupt-map property.
72 *
73 * interrupt-parent
74 * A single <phandle> value that points to the interrupt parent to
75 * which the child domain is being mapped.
76 *
77 * parent unit address
78 * The unit address in the domain of the interrupt parent. The number
79 * of 32-bit cells required to specify this address is described by the
80 * #address-cells property of the node pointed to by the
81 * interrupt-parent field.
82 *
83 * parent interrupt specifier
84 * The interrupt specifier in the parent domain. The number of 32-bit
85 * cells required to specify this component is described by the
86 * #interrupt-cells property of the node pointed to by the
87 * interrupt-parent field.
88 *
89 * Lookups are performed on the interrupt mapping table by matching a
90 * unit-address/interrupt specifier pair against the child components in
91 * the interrupt-map. Because some fields in the unit interrupt specifier
92 * may not be relevant, a mask is applied before the lookup is done.
93 * Example:
94 *
95 * pic: interrupt-controller@0 {
96 * interrupt-controller;
97 * #address-cells = <0>; // icaddr (parent unit address)
98 * #interrupt-cells = <1>; // icintr (parent interrupt specifier)
99 * };
100 *
101 * gic: interrupt-controller@1 {
102 * interrupt-controller;
103 * #address-cells = <2>; // icaddr (parent unit address)
104 * #interrupt-cells = <3>; // icintr (parent interrupt specifier)
105 * };
106 *
107 * pcie {
108 * #address-cells = <3>; // addr (child unit address)
109 * #interrupt-cells = <1>; // pin (child interrupt specifier)
110 * interrupt-parent = <&gic>;
111 * interrupt-map-mask = <0x1800 0 0 7>;
112 * interrupt-map =
113 * // addr pin ic icintr
114 * <0x0000 0 0 1 &pic 1>, // INTA SOLT 0
115 * <0x0000 0 0 2 &pic 2>, // INTB
116 * <0x0000 0 0 3 &pic 3>, // INTC
117 * <0x0000 0 0 4 &pic 4>, // INTD
118 * <0x0800 0 0 1 &pic 2>, // INTA SOLT 1
119 * <0x0800 0 0 2 &pic 3>, // INTB
120 * <0x0800 0 0 3 &pic 4>, // INTC
121 * <0x0800 0 0 4 &pic 1>, // INTD
122 * // addr pin ic icaddr icintr
123 * <0x1000 0 0 1 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, // INTA SOLT 2
124 * <0x1000 0 0 2 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, // INTB
125 * <0x1000 0 0 3 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, // INTC
126 * <0x1000 0 0 4 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, // INTD
127 * <0x1800 0 0 1 &gic 0 0 GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, // INTA SOLT 3
128 * <0x1800 0 0 2 &gic 0 0 GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>, // INTB
129 * <0x1800 0 0 3 &gic 0 0 GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>, // INTC
130 * <0x1800 0 0 4 &gic 0 0 GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; // INTD
131 * };
132 *
133 * In fact, almost no SoC will be use multi IC to implement INTx.
134 * before call ofw_parse_irq_map(np, &args):
135 *
136 * args.data = addr;
137 * args.args_count = 2 or 3;
138 * args.args[0] = (addr cells);
139 * args.args[1] = (pin cells);
140 * args.args[2] = (icaddr cells);
141 *
142 * if call with `pcie` in ofw_parse_irq_map(np, &args):
143 *
144 * np = &pcie;
145 * args.data = addr = fdt32_t({ (bus << 16) | (device << 11) | (function << 8), 0, 0, pin });
146 * args.args_count = 2;
147 * args.args[0] = 3;
148 * args.args[1] = 1;
149 *
150 * To perform a lookup of the gic interrupt source number for INTB for IDSEL
151 * 0x12 (slot 2), function 0x3, the following steps would be performed:
152 *
153 * 1.The user addr is value <0x9300 0 0 2>.
154 *
155 * 2.The encoding of the address includes the bus number (0x0 << 16),
156 * device number (0x12 << 11), and function number (0x3 << 8).
157 *
158 * 3.The interrupt specifier is 2, which is the encoding for INTB as per
159 * the PCI binding.
160 *
161 * 4.The interrupt-map-mask value <0x1800 0 0 7> is applied, giving a
162 * result of <0x1000 0 0 2>.
163 *
164 * 5.That result is looked up in the interrupt-map table, which maps to the
165 * parent interrupt specifier <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>.
166 */
167
168 do {
169 err = -RT_EEMPTY;
170
171 if ((child_address_cells = rt_ofw_bus_addr_cells(np)) < 0)
172 {
173 LOG_D("%s property %s is undefined", np->full_name, "#address-cells");
174
175 break;
176 }
177
178 if ((child_interrupt_cells = ofw_interrupt_cells(np)) < 0)
179 {
180 LOG_D("%s property %s is undefined", np->full_name, "#interrupt-cells");
181
182 break;
183 }
184
185 if (!(map = rt_ofw_prop_read_raw(np, "interrupt-map", &map_len)))
186 {
187 LOG_D("%s property %s is undefined", np->full_name, "interrupt-map");
188
189 break;
190 }
191
192 if (!(map_mask = rt_ofw_prop_read_raw(np, "interrupt-map-mask", &map_mask_len)))
193 {
194 LOG_D("%s property %s is undefined", np->full_name, "interrupt-map-mask");
195
196 break;
197 }
198
199 map_len /= sizeof(fdt32_t);
200 map_mask_len /= sizeof(fdt32_t);
201
202 err = -RT_EINVAL;
203
204 addr = irq_args->data;
205 addr_cells = irq_args->args[0];
206 pin_cells = irq_args->args[1];
207 icaddr_cells = irq_args->args_count == 3 ? irq_args->args[2] : 0;
208
209 if (addr_cells > child_address_cells)
210 {
211 LOG_D("%s(%d) > %s(%d)", "addr_cells", addr_cells, "child_address_cells", child_address_cells);
212
213 break;
214 }
215
216 if (pin_cells > child_interrupt_cells)
217 {
218 LOG_D("%s(%d) > %s(%d)", "pin_cells", pin_cells, "child_interrupt_cells", child_interrupt_cells);
219
220 break;
221 }
222
223 err = -RT_ENOENT;
224
225 #define _map_walk_range(_idx, _idx2, _count, ...) \
226 for (idx1 = _idx, idx2 = _idx2, limit = idx1 + _count; idx1 < limit __VA_ARGS__; ++idx1, ++idx2)
227
228 _map_walk_range(0, 0, addr_cells)
229 {
230 /* Applied addr mask */
231 ((fdt32_t *)addr)[idx1] &= map_mask[idx2];
232 }
233
234 _map_walk_range(addr_cells, child_address_cells, pin_cells)
235 {
236 /* Applied pin mask */
237 ((fdt32_t *)addr)[idx1] &= map_mask[idx2];
238 }
239
240 while (map_len > 0)
241 {
242 rt_bool_t match = RT_TRUE;
243
244 _map_walk_range(0, 0, addr_cells)
245 {
246 /* Applied mask */
247 if (addr[idx1] != map[idx2])
248 {
249 match = RT_FALSE;
250 break;
251 }
252 }
253
254 _map_walk_range(addr_cells, child_address_cells, pin_cells, && match)
255 {
256 /* Applied mask */
257 if (addr[idx1] != map[idx2])
258 {
259 match = RT_FALSE;
260 break;
261 }
262 }
263
264 /* Skip addr, pin */
265 map += map_mask_len;
266
267 /* IC is different? */
268 if (ic_phandle != fdt32_to_cpu(*map))
269 {
270 rt_ofw_node_put(ic_np);
271
272 ic_phandle = fdt32_to_cpu(*map);
273 ic_np = rt_ofw_find_node_by_phandle(ic_phandle);
274
275 if (!ic_np)
276 {
277 LOG_D("%s irq parent phandle = %d is not found", np->full_name, ic_phandle);
278
279 break;
280 }
281
282 if ((parent_address_cells = rt_ofw_bus_addr_cells(ic_np)) < 0)
283 {
284 LOG_D("%s property %s is undefined", ic_np->full_name, "#address-cells");
285
286 break;
287 }
288
289 if (icaddr_cells > parent_address_cells)
290 {
291 LOG_D("%s(%d) > %s(%d)", "icaddr_cells", icaddr_cells, "parent_address_cells", parent_address_cells);
292
293 break;
294 }
295
296 if ((parent_interrupt_cells = ofw_interrupt_cells(ic_np)) < 0)
297 {
298 LOG_D("%s property %s is undefined", ic_np->full_name, "#interrupt-cells");
299
300 break;
301 }
302
303 RT_ASSERT(parent_interrupt_cells <= RT_OFW_MAX_CELL_ARGS);
304 }
305
306 /* Skip ic phandle */
307 ++map;
308
309 _map_walk_range(addr_cells + pin_cells, 0, icaddr_cells, && match)
310 {
311 /* Applied ic_addr mask */
312 if (addr[idx1] != map[idx2])
313 {
314 match = RT_FALSE;
315 break;
316 }
317 }
318
319 /* Skip icaddr */
320 map += parent_address_cells;
321
322 if (match)
323 {
324 irq_args->data = ic_np;
325 irq_args->args_count = parent_interrupt_cells;
326
327 for (int i = 0; i < irq_args->args_count; ++i)
328 {
329 irq_args->args[i] = fdt32_to_cpu(*map++);
330 }
331
332 err = RT_EOK;
333
334 break;
335 }
336
337 /* Skip icintr */
338 map += parent_interrupt_cells;
339
340 map_len -= map_mask_len + 1 + parent_address_cells + parent_interrupt_cells;
341 }
342
343 #undef _map_walk_range
344 } while (0);
345
346 return err;
347 }
348
rt_ofw_parse_irq_map(struct rt_ofw_node * np,struct rt_ofw_cell_args * irq_args)349 rt_err_t rt_ofw_parse_irq_map(struct rt_ofw_node *np, struct rt_ofw_cell_args *irq_args)
350 {
351 rt_err_t err;
352
353 if (np && irq_args && irq_args->data)
354 {
355 err = ofw_parse_irq_map(np, irq_args);
356 }
357 else
358 {
359 err = -RT_EINVAL;
360 }
361
362 return err;
363 }
364
ofw_parse_irq_cells(struct rt_ofw_node * np,int index,struct rt_ofw_cell_args * out_irq_args)365 static rt_err_t ofw_parse_irq_cells(struct rt_ofw_node *np, int index, struct rt_ofw_cell_args *out_irq_args)
366 {
367 rt_err_t err;
368
369 /*
370 * interrupts-extended:
371 *
372 * The interrupts-extended property lists the interrupt(s) generated by a
373 * device. interrupts-extended should be used instead of interrupts when a
374 * device is connected to multiple interrupt controllers as it encodes a
375 * parent phandle with each interrupt specifier. Example:
376 *
377 * pic: interrupt-controller@0 {
378 * interrupt-controller;
379 * #interrupt-cells = <1>;
380 * };
381 *
382 * gic: interrupt-controller@1 {
383 * interrupt-controller;
384 * #interrupt-cells = <3>;
385 * };
386 *
387 * node: node {
388 * interrupts-extended = <&pic 9>, <&gic GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
389 * };
390 *
391 * call `rt_ofw_parse_phandle_cells` to get irq info;
392 */
393
394 err = rt_ofw_parse_phandle_cells(np, "interrupts-extended", "#interrupt-cells", index, out_irq_args);
395
396 do {
397 int interrupt_cells;
398 const fdt32_t *cell;
399 rt_ssize_t interrupt_len;
400 struct rt_ofw_node *ic_np;
401
402 if (!err)
403 {
404 break;
405 }
406
407 /*
408 * interrupts (old style):
409 *
410 * The interrupts property of a device node defines the interrupt or
411 * interrupts that are generated by the device. The value of the
412 * interrupts property consists of an arbitrary number of interrupt
413 * specifiers. The format of an interrupt specifier is defined by the
414 * binding of the interrupt domain root.
415 * interrupts is overridden by the interrupts-extended property and
416 * normally only one or the other should be used. Example:
417 *
418 * pic: interrupt-controller@0 {
419 * interrupt-controller;
420 * #interrupt-cells = <1>;
421 * };
422 *
423 * gic: interrupt-controller@1 {
424 * interrupt-controller;
425 * #interrupt-cells = <3>;
426 * };
427 *
428 * node0: node0 {
429 * interrupt-parent = <&pic>;
430 * interrupts = <9>;
431 * };
432 *
433 * node1: node1 {
434 * interrupt-parent = <&gic>;
435 * interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
436 * };
437 */
438
439 cell = rt_ofw_prop_read_raw(np, "interrupts", &interrupt_len);
440
441 if (!cell)
442 {
443 err = -RT_ERROR;
444 break;
445 }
446
447 ic_np = rt_ofw_find_irq_parent(np, &interrupt_cells);
448
449 if (!ic_np)
450 {
451 err = -RT_ERROR;
452 break;
453 }
454
455 RT_ASSERT(interrupt_cells <= RT_OFW_MAX_CELL_ARGS);
456
457 if (index >= interrupt_len / (interrupt_cells * sizeof(*cell)))
458 {
459 err = -RT_EINVAL;
460 break;
461 }
462
463 cell += index * interrupt_cells;
464
465 out_irq_args->data = ic_np;
466 out_irq_args->args_count = interrupt_cells;
467
468 for (int idx = 0; idx < interrupt_cells; ++idx, ++cell)
469 {
470 out_irq_args->args[idx] = fdt32_to_cpu(*cell);
471 }
472
473 err = RT_EOK;
474 } while (0);
475
476 return err;
477 }
478
rt_ofw_parse_irq_cells(struct rt_ofw_node * np,int index,struct rt_ofw_cell_args * out_irq_args)479 rt_err_t rt_ofw_parse_irq_cells(struct rt_ofw_node *np, int index, struct rt_ofw_cell_args *out_irq_args)
480 {
481 rt_err_t err;
482
483 if (np && index >= 0 && out_irq_args)
484 {
485 err = ofw_parse_irq_cells(np, index, out_irq_args);
486 }
487 else
488 {
489 err = -RT_EINVAL;
490 }
491
492 return err;
493 }
494
rt_ofw_find_irq_parent(struct rt_ofw_node * np,int * out_interrupt_cells)495 struct rt_ofw_node *rt_ofw_find_irq_parent(struct rt_ofw_node *np, int *out_interrupt_cells)
496 {
497 for (np = rt_ofw_node_get(np); np; np = rt_ofw_get_next_parent(np))
498 {
499 rt_phandle ic_phandle;
500
501 if (!rt_ofw_prop_read_u32(np, "interrupt-parent", (rt_uint32_t *)&ic_phandle))
502 {
503 int interrupt_cells;
504 struct rt_ofw_node *ic_np = rt_ofw_find_node_by_phandle(ic_phandle);
505
506 if (ic_np && (interrupt_cells = ofw_interrupt_cells(ic_np)) >= 0)
507 {
508 np = ic_np;
509
510 if (out_interrupt_cells)
511 {
512 *out_interrupt_cells = interrupt_cells;
513 }
514
515 break;
516 }
517
518 rt_ofw_node_put(ic_np);
519 }
520 }
521
522 return np;
523 }
524
ofw_map_irq(struct rt_ofw_cell_args * irq_args)525 static int ofw_map_irq(struct rt_ofw_cell_args *irq_args)
526 {
527 int irq;
528 struct rt_ofw_node *ic_np = irq_args->data;
529 struct rt_pic *pic = rt_pic_dynamic_cast(rt_ofw_data(ic_np));
530
531 /* args.data is "interrupt-controller" */
532 if (pic)
533 {
534 struct rt_pic_irq pirq;
535
536 if (!pic->ops->irq_parse)
537 {
538 LOG_E("Master pic MUST implemented irq_parse");
539 RT_ASSERT(0);
540 }
541
542 if (!pic->ops->irq_map)
543 {
544 LOG_E("Master pic MUST implemented irq_map");
545 RT_ASSERT(0);
546 }
547
548 irq = pic->ops->irq_parse(pic, irq_args, &pirq);
549
550 if (!irq)
551 {
552 irq = pic->ops->irq_map(pic, pirq.hwirq, pirq.mode);
553 }
554 }
555 else
556 {
557 LOG_E("Master pic %s not support", ic_np->full_name);
558 irq = -RT_EIO;
559 }
560
561 rt_ofw_node_put(ic_np);
562
563 return irq;
564 }
565
rt_ofw_map_irq(struct rt_ofw_cell_args * irq_args)566 int rt_ofw_map_irq(struct rt_ofw_cell_args *irq_args)
567 {
568 int irq;
569
570 if (irq_args && irq_args->data && irq_args->args_count > 0)
571 {
572 irq = ofw_map_irq(irq_args);
573 }
574 else
575 {
576 irq = -RT_EINVAL;
577 }
578
579 return irq;
580 }
581
rt_ofw_get_irq_count(struct rt_ofw_node * np)582 int rt_ofw_get_irq_count(struct rt_ofw_node *np)
583 {
584 int count;
585
586 if (np)
587 {
588 struct rt_ofw_cell_args irq_args;
589
590 count = 0;
591
592 while (!ofw_parse_irq_cells(np, count, &irq_args))
593 {
594 ++count;
595 }
596 }
597 else
598 {
599 count = -RT_EINVAL;
600 }
601
602 return count;
603 }
604
rt_ofw_get_irq(struct rt_ofw_node * np,int index)605 int rt_ofw_get_irq(struct rt_ofw_node *np, int index)
606 {
607 int irq;
608
609 if (np && index >= 0)
610 {
611 struct rt_ofw_cell_args irq_args;
612
613 irq = ofw_parse_irq_cells(np, index, &irq_args);
614
615 if (irq >= 0)
616 {
617 rt_phandle cpu_phandle;
618
619 irq = ofw_map_irq(&irq_args);
620
621 if (irq >= 0 && !rt_ofw_prop_read_u32_index(np, "interrupt-affinity", index, &cpu_phandle))
622 {
623 rt_uint64_t cpuid = rt_ofw_get_cpu_id(rt_ofw_find_node_by_phandle(cpu_phandle));
624
625 if ((rt_int64_t)cpuid >= 0)
626 {
627 RT_BITMAP_DECLARE(affinity, RT_CPUS_NR) = { 0 };
628
629 rt_bitmap_set_bit(affinity, cpuid);
630
631 if (rt_pic_irq_set_affinity(irq, affinity) == -RT_ENOSYS)
632 {
633 LOG_W("%s irq affinity init fail", np->full_name);
634 }
635 }
636 }
637 }
638 }
639 else
640 {
641 irq = -RT_EINVAL;
642 }
643
644 return irq;
645 }
646
rt_ofw_get_irq_by_name(struct rt_ofw_node * np,const char * name)647 int rt_ofw_get_irq_by_name(struct rt_ofw_node *np, const char *name)
648 {
649 int irq;
650
651 if (np && name)
652 {
653 int index = rt_ofw_prop_index_of_string(np, "interrupt-names", name);
654
655 if (index >= 0)
656 {
657 irq = rt_ofw_get_irq(np, index);
658 }
659 else
660 {
661 irq = -1;
662 }
663 }
664 else
665 {
666 irq = -RT_EINVAL;
667 }
668
669 return irq;
670 }
671