1 /*
2  * Copyright (c) 2006-2024 RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2024-10-08     zhujiale    the first version
9  */
10 #ifndef __PHY_MDIO_H__
11 #define __PHY_MDIO_H__
12 #include <rtthread.h>
13 #include <rtdevice.h>
14 
15 #define RT_MDIO_DEVAD_NONE          (-1)
16 #define RT_MDIO_MMD_PMAPMD  1   /* Physical Medium Attachment/
17                      * Physical Medium Dependent */
18 #define RT_MDIO_MMD_WIS     2   /* WAN Interface Sublayer */
19 #define RT_MDIO_MMD_PCS     3   /* Physical Coding Sublayer */
20 #define RT_MDIO_MMD_PHYXS   4   /* PHY Extender Sublayer */
21 #define RT_MDIO_MMD_DTEXS   5   /* DTE Extender Sublayer */
22 #define RT_MDIO_MMD_TC      6   /* Transmission Convergence */
23 #define RT_MDIO_MMD_AN      7   /* Auto-Negotiation */
24 #define RT_MDIO_MMD_C22EXT  29  /* Clause 22 extension */
25 #define RT_MDIO_MMD_VEND1   30  /* Vendor specific 1 */
26 #define RT_MDIO_MMD_VEND2   31  /* Vendor specific 2 */
27 
28 #define RT_MII_BMCR         0x00    /* Basic mode control register */
29 #define RT_MII_BMSR         0x01    /* Basic mode status register  */
30 #define RT_MII_PHYSID1      0x02    /* PHYS ID 1                   */
31 #define RT_MII_PHYSID2      0x03    /* PHYS ID 2                   */
32 #define RT_MII_ADVERTISE    0x04    /* Advertisement control reg   */
33 #define RT_MII_LPA          0x05    /* Link partner ability reg    */
34 #define RT_MII_EXPANSION    0x06    /* Expansion register          */
35 #define RT_MII_CTRL1000     0x09    /* 1000BASE-T control          */
36 #define RT_MII_STAT1000     0x0a    /* 1000BASE-T status           */
37 #define RT_MII_MMD_CTRL     0x0d    /* MMD Access Control Register */
38 #define RT_MII_MMD_DATA     0x0e    /* MMD Access Data Register */
39 #define RT_MII_ESTATUS      0x0f    /* Extended Status             */
40 #define RT_MII_DCOUNTER     0x12    /* Disconnect counter          */
41 #define RT_MII_FCSCOUNTER   0x13    /* False carrier counter       */
42 #define RT_MII_NWAYTEST     0x14    /* N-way auto-neg test reg     */
43 #define RT_MII_RERRCOUNTER  0x15    /* Receive error counter       */
44 #define RT_MII_SREVISION    0x16    /* Silicon revision            */
45 #define RT_MII_RESV1        0x17    /* Reserved...                 */
46 #define RT_MII_LBRERROR     0x18    /* Lpback, rx, bypass error    */
47 #define RT_MII_PHYADDR      0x19    /* PHY address                 */
48 #define RT_MII_RESV2        0x1a    /* Reserved...                 */
49 #define RT_MII_TPISTATUS    0x1b    /* TPI status for 10mbps       */
50 #define RT_MII_NCONFIG      0x1c    /* Network interface config    */
51 
52 /* Basic mode control register. */
53 #define RT_BMCR_RESV            0x003f  /* Unused...                   */
54 #define RT_BMCR_SPEED1000       0x0040  /* MSB of Speed (1000)         */
55 #define RT_BMCR_CTST            0x0080  /* Collision test              */
56 #define RT_BMCR_FULLDPLX        0x0100  /* Full duplex                 */
57 #define RT_BMCR_ANRESTART       0x0200  /* Auto negotiation restart    */
58 #define RT_BMCR_ISOLATE         0x0400  /* Isolate data paths from MII */
59 #define RT_BMCR_PDOWN           0x0800  /* Enable low power state      */
60 #define RT_BMCR_ANENABLE        0x1000  /* Enable auto negotiation     */
61 #define RT_BMCR_SPEED100        0x2000  /* Select 100Mbps              */
62 #define RT_BMCR_LOOPBACK        0x4000  /* TXD loopback bits           */
63 #define RT_BMCR_RESET           0x8000  /* Reset to default state      */
64 #define RT_BMCR_SPEED10         0x0000  /* Select 10Mbps               */
65 
66 #define RT_MII_MMD_CTRL_DEVAD_MASK  0x1f    /* Mask MMD DEVAD*/
67 #define RT_MII_MMD_CTRL_ADDR        0x0000  /* Address */
68 #define RT_MII_MMD_CTRL_NOINCR      0x4000  /* no post increment */
69 #define RT_MII_MMD_CTRL_INCR_RDWT   0x8000  /* post increment on reads & writes */
70 #define RT_MII_MMD_CTRL_INCR_ON_WT  0xC000  /* post increment on writes only */
71 
72 
73 #define RT_PHY_MAX 32
74 
75 struct mii_bus
76 {
77     struct rt_list_node node;
78     char name[RT_NAME_MAX];
79     void* priv;
80     int (*read)(struct mii_bus* bus, int addr, int devad, int reg);
81     int (*write)(struct mii_bus* bus, int addr, int devad, int reg, rt_uint16_t val);
82     /** @read_c45: Perform a C45 read transfer on the bus */
83     int (*read_c45)(struct mii_bus* bus, int addr, int devad, int reg);
84     /** @write_c45: Perform a C45 write transfer on the bus */
85     int (*write_c45)(struct mii_bus* bus, int addr, int devad, int reg, rt_uint16_t val);
86     int (*reset)(struct mii_bus* bus);
87     struct rt_phy_device* phymap[RT_PHY_MAX];
88     rt_uint32_t phy_mask;
89     int reset_delay_us;
90     int reset_post_delay_us;
91 };
92 
93 rt_err_t rt_mdio_register(struct mii_bus* bus);
94 rt_err_t rt_mdio_unregister(struct mii_bus* bus);
95 
96 struct mii_bus* rt_mdio_get_bus_by_name(const char* busname);
97 struct mii_bus* rt_mdio_alloc(void);
98 #endif
99