1 /*
2 * Copyright (c) 2024, sakumisu
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include "usbh_core.h"
7 #include "usbh_asix.h"
8 #include "usb_cdc.h"
9
10 #undef USB_DBG_TAG
11 #define USB_DBG_TAG "asix"
12 #include "usb_log.h"
13
14 #define DEV_FORMAT "/dev/asix"
15
16 static struct usbh_asix g_asix_class;
17
18 static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_rx_buffer[USB_ALIGN_UP(CONFIG_USBHOST_ASIX_ETH_MAX_TX_SIZE, CONFIG_USB_ALIGN_SIZE)];
19 static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_tx_buffer[USB_ALIGN_UP(CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE, CONFIG_USB_ALIGN_SIZE)];
20 static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_inttx_buffer[USB_ALIGN_UP(16, CONFIG_USB_ALIGN_SIZE)];
21
22 static USB_NOCACHE_RAM_SECTION USB_MEM_ALIGNX uint8_t g_asix_buf[USB_ALIGN_UP(32, CONFIG_USB_ALIGN_SIZE)];
23
24 #define ETH_ALEN 6
25
26 #define PHY_MODE_MARVELL 0x0000
27 #define MII_MARVELL_LED_CTRL 0x0018
28 #define MII_MARVELL_STATUS 0x001b
29 #define MII_MARVELL_CTRL 0x0014
30
31 #define MARVELL_LED_MANUAL 0x0019
32
33 #define MARVELL_STATUS_HWCFG 0x0004
34
35 #define MARVELL_CTRL_TXDELAY 0x0002
36 #define MARVELL_CTRL_RXDELAY 0x0080
37
38 #define PHY_MODE_RTL8211CL 0x000C
39
40 #define AX88772A_PHY14H 0x14
41 #define AX88772A_PHY14H_DEFAULT 0x442C
42
43 #define AX88772A_PHY15H 0x15
44 #define AX88772A_PHY15H_DEFAULT 0x03C8
45
46 #define AX88772A_PHY16H 0x16
47 #define AX88772A_PHY16H_DEFAULT 0x4044
48
49 #define SPEED_100 0
50 #define SPEED_10 1
51
usbh_asix_read_cmd(struct usbh_asix * asix_class,uint8_t cmd,uint16_t value,uint16_t index,void * data,uint16_t size)52 static int usbh_asix_read_cmd(struct usbh_asix *asix_class,
53 uint8_t cmd,
54 uint16_t value,
55 uint16_t index,
56 void *data,
57 uint16_t size)
58 {
59 struct usb_setup_packet *setup;
60 int ret;
61
62 if (!asix_class || !asix_class->hport) {
63 return -USB_ERR_INVAL;
64 }
65 setup = asix_class->hport->setup;
66
67 setup->bmRequestType = USB_REQUEST_DIR_IN | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE;
68 setup->bRequest = cmd;
69 setup->wValue = value;
70 setup->wIndex = index;
71 setup->wLength = size;
72
73 ret = usbh_control_transfer(asix_class->hport, setup, g_asix_buf);
74 if (ret < 8) {
75 return ret;
76 }
77 memcpy(data, g_asix_buf, MIN(ret - 8, size));
78
79 return ret;
80 }
81
usbh_asix_write_cmd(struct usbh_asix * asix_class,uint8_t cmd,uint16_t value,uint16_t index,void * data,uint16_t size)82 static int usbh_asix_write_cmd(struct usbh_asix *asix_class,
83 uint8_t cmd,
84 uint16_t value,
85 uint16_t index,
86 void *data,
87 uint16_t size)
88 {
89 struct usb_setup_packet *setup;
90
91 if (!asix_class || !asix_class->hport) {
92 return -USB_ERR_INVAL;
93 }
94 setup = asix_class->hport->setup;
95
96 setup->bmRequestType = USB_REQUEST_DIR_OUT | USB_REQUEST_VENDOR | USB_REQUEST_RECIPIENT_DEVICE;
97 setup->bRequest = cmd;
98 setup->wValue = value;
99 setup->wIndex = index;
100 setup->wLength = size;
101
102 if (data && size) {
103 memcpy(g_asix_buf, data, size);
104 return usbh_control_transfer(asix_class->hport, setup, g_asix_buf);
105 } else {
106 return usbh_control_transfer(asix_class->hport, setup, NULL);
107 }
108 }
109
usbh_asix_mdio_write(struct usbh_asix * asix_class,int phy_id,int loc,int val)110 static int usbh_asix_mdio_write(struct usbh_asix *asix_class, int phy_id, int loc, int val)
111 {
112 uint8_t smsr;
113 uint16_t res = (uint16_t)val;
114 int ret;
115
116 for (uint8_t i = 0; i < 10; i++) {
117 ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_SW_MII, 0, 0, NULL, 0);
118 if (ret < 0) {
119 return ret;
120 }
121 usb_osal_msleep(1);
122 ret = usbh_asix_read_cmd(asix_class, AX_CMD_STATMNGSTS_REG, 0, 0, &smsr, 1);
123 if (ret < 0) {
124 return ret;
125 }
126
127 if (smsr & AX_HOST_EN) {
128 break;
129 }
130 }
131
132 ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_MII_REG, phy_id, loc, &res, 2);
133 if (ret < 0) {
134 return ret;
135 }
136
137 ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_HW_MII, 0, 0, NULL, 0);
138 if (ret < 0) {
139 return ret;
140 }
141 return 0;
142 }
143
usbh_asix_mdio_read(struct usbh_asix * asix_class,int phy_id,int loc)144 static int usbh_asix_mdio_read(struct usbh_asix *asix_class, int phy_id, int loc)
145 {
146 uint8_t smsr;
147 uint16_t res;
148 int ret;
149
150 for (uint8_t i = 0; i < 10; i++) {
151 ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_SW_MII, 0, 0, NULL, 0);
152 if (ret < 0) {
153 return ret;
154 }
155 usb_osal_msleep(1);
156 ret = usbh_asix_read_cmd(asix_class, AX_CMD_STATMNGSTS_REG, 0, 0, &smsr, 1);
157 if (ret < 0) {
158 return ret;
159 }
160
161 if (smsr & AX_HOST_EN) {
162 break;
163 }
164 }
165
166 ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_MII_REG, phy_id, loc, &res, 2);
167 if (ret < 0) {
168 return ret;
169 }
170
171 ret = usbh_asix_write_cmd(asix_class, AX_CMD_SET_HW_MII, 0, 0, NULL, 0);
172 if (ret < 0) {
173 return ret;
174 }
175 return res;
176 }
177
usbh_asix_read_phy_addr(struct usbh_asix * asix_class,bool internal)178 static int usbh_asix_read_phy_addr(struct usbh_asix *asix_class, bool internal)
179 {
180 int ret, offset;
181 uint8_t buf[2];
182
183 ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_PHY_ID, 0, 0, buf, 2);
184 if (ret < 0) {
185 return ret;
186 }
187
188 offset = (internal ? 1 : 0);
189 ret = buf[offset];
190
191 USB_LOG_INFO("%s PHY address 0x%x\r\n", internal ? "internal" : "external", ret);
192
193 return ret;
194 }
195
usbh_asix_sw_reset(struct usbh_asix * asix_class,uint8_t flags)196 static int usbh_asix_sw_reset(struct usbh_asix *asix_class, uint8_t flags)
197 {
198 int ret;
199
200 ret = usbh_asix_write_cmd(asix_class, AX_CMD_SW_RESET, flags, 0, NULL, 0);
201 if (ret < 0)
202 USB_LOG_ERR("Failed to send software reset: %d\r\n", ret);
203
204 return ret;
205 }
206
usbh_asix_read_rx_ctl(struct usbh_asix * asix_class)207 static uint16_t usbh_asix_read_rx_ctl(struct usbh_asix *asix_class)
208 {
209 uint16_t v;
210 int ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_RX_CTL, 0, 0, &v, 2);
211 if (ret < 0) {
212 return ret;
213 }
214 return v;
215 }
216
usbh_asix_write_rx_ctl(struct usbh_asix * asix_class,uint16_t mode)217 static int usbh_asix_write_rx_ctl(struct usbh_asix *asix_class, uint16_t mode)
218 {
219 int ret;
220
221 USB_LOG_DBG("asix_write_rx_ctl() - mode = 0x%04x\r\n", mode);
222 ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_RX_CTL, mode, 0, NULL, 0);
223 if (ret < 0)
224 USB_LOG_ERR("Failed to write RX_CTL mode to 0x%04x: %02x\r\n",
225 mode, ret);
226
227 return ret;
228 }
229
usbh_asix_read_medium_status(struct usbh_asix * asix_class)230 static uint16_t usbh_asix_read_medium_status(struct usbh_asix *asix_class)
231 {
232 uint16_t v;
233 int ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_MEDIUM_STATUS, 0, 0, &v, 2);
234
235 if (ret < 0) {
236 USB_LOG_ERR("Error reading Medium Status register: %02x\r\n",
237 ret);
238 return ret; /* TODO: callers not checking for error ret */
239 }
240
241 return v;
242 }
243
usbh_asix_write_medium_mode(struct usbh_asix * asix_class,uint16_t mode)244 static int usbh_asix_write_medium_mode(struct usbh_asix *asix_class, uint16_t mode)
245 {
246 int ret;
247
248 USB_LOG_DBG("asix_write_medium_mode() - mode = 0x%04x\r\n", mode);
249 ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_MEDIUM_MODE, mode, 0, NULL, 0);
250 if (ret < 0)
251 USB_LOG_ERR("Failed to write Medium Mode mode to 0x%04x: %02x\r\n",
252 mode, ret);
253
254 return ret;
255 }
256
usbh_asix_write_gpio(struct usbh_asix * asix_class,uint16_t value,int sleep)257 static int usbh_asix_write_gpio(struct usbh_asix *asix_class, uint16_t value, int sleep)
258 {
259 int ret;
260
261 USB_LOG_DBG("asix_write_gpio() - value = 0x%04x\r\n", value);
262 ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_GPIOS, value, 0, NULL, 0);
263 if (ret < 0)
264 USB_LOG_ERR("Failed to write GPIO value 0x%04x: %d\r\n",
265 value, ret);
266
267 if (sleep)
268 usb_osal_msleep(sleep);
269
270 return ret;
271 }
272
273 /*
274 * AX88772 & AX88178 have a 16-bit RX_CTL value
275 */
usbh_asix_set_multicast(struct usbh_asix * asix_class)276 static void usbh_asix_set_multicast(struct usbh_asix *asix_class)
277 {
278 uint16_t rx_ctl = AX_DEFAULT_RX_CTL | AX_RX_CTL_AM;
279 #if CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE == 4096
280 rx_ctl |= AX_RX_CTL_MFB_4096;
281 #elif CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE == 8192
282 rx_ctl |= AX_RX_CTL_MFB_8192;
283 #elif CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE == 16384
284 rx_ctl |= AX_RX_CTL_MFB_16384;
285 #else
286 rx_ctl |= AX_RX_CTL_MFB_2048;
287 #endif
288 const uint8_t multi_filter[] = { 0x00, 0x00, 0x20, 0x80, 0x00, 0x00, 0x00, 0x40 };
289
290 usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_MULTI_FILTER, 0, 0, (uint8_t *)multi_filter, AX_MCAST_FILTER_SIZE);
291 usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_RX_CTL, rx_ctl, 0, NULL, 0);
292 }
293
usbh_ax88772_hw_reset(struct usbh_asix * asix_class)294 static int usbh_ax88772_hw_reset(struct usbh_asix *asix_class)
295 {
296 uint16_t rx_ctl;
297 int ret;
298
299 ret = usbh_asix_write_gpio(asix_class, AX_GPIO_RSE | AX_GPIO_GPO_2 | AX_GPIO_GPO2EN, 5);
300 if (ret < 0)
301 goto out;
302
303 ret = usbh_asix_write_cmd(asix_class, AX_CMD_SW_PHY_SELECT, asix_class->embd_phy,
304 0, NULL, 0);
305 if (ret < 0) {
306 USB_LOG_ERR("Select PHY #1 failed: %d\r\n", ret);
307 goto out;
308 }
309
310 if (asix_class->embd_phy) {
311 ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPPD);
312 if (ret < 0)
313 goto out;
314
315 usb_osal_msleep(10);
316
317 ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_CLEAR);
318 if (ret < 0)
319 goto out;
320
321 usb_osal_msleep(60);
322
323 ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPRL | AX_SWRESET_PRL);
324 if (ret < 0)
325 goto out;
326 } else {
327 ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPPD | AX_SWRESET_PRL);
328 if (ret < 0)
329 goto out;
330 }
331
332 usb_osal_msleep(150);
333
334 ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL);
335 if (ret < 0)
336 goto out;
337
338 ret = usbh_asix_write_medium_mode(asix_class, AX88772_MEDIUM_DEFAULT);
339 if (ret < 0)
340 goto out;
341
342 ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_IPG0,
343 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
344 AX88772_IPG2_DEFAULT, NULL, 0);
345 if (ret < 0) {
346 USB_LOG_ERR("Write IPG,IPG1,IPG2 failed: %d\r\n", ret);
347 goto out;
348 }
349
350 /* Rewrite MAC address */
351 ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_NODE_ID, 0, 0, asix_class->mac, ETH_ALEN);
352 if (ret < 0)
353 goto out;
354
355 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
356 ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL);
357 if (ret < 0)
358 goto out;
359
360 rx_ctl = usbh_asix_read_rx_ctl(asix_class);
361 USB_LOG_INFO("RX_CTL is 0x%04x after all initializations\r\n",
362 rx_ctl);
363
364 rx_ctl = usbh_asix_read_medium_status(asix_class);
365 USB_LOG_INFO("Medium Status is 0x%04x after all initializations\r\n",
366 rx_ctl);
367
368 return 0;
369
370 out:
371 return ret;
372 }
373
usbh_ax88772a_hw_reset(struct usbh_asix * asix_class)374 static int usbh_ax88772a_hw_reset(struct usbh_asix *asix_class)
375 {
376 uint16_t rx_ctl, phy14h, phy15h, phy16h;
377 int ret;
378
379 ret = usbh_asix_write_gpio(asix_class, AX_GPIO_RSE, 5);
380 if (ret < 0)
381 goto out;
382
383 ret = usbh_asix_write_cmd(asix_class, AX_CMD_SW_PHY_SELECT, asix_class->embd_phy | AX_PHYSEL_SSEN, 0, NULL, 0);
384 if (ret < 0) {
385 USB_LOG_ERR("Select PHY #1 failed: %d\r\n", ret);
386 goto out;
387 }
388 usb_osal_msleep(10);
389
390 ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPPD | AX_SWRESET_IPRL);
391 if (ret < 0)
392 goto out;
393
394 usb_osal_msleep(10);
395
396 ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPRL);
397 if (ret < 0)
398 goto out;
399
400 usb_osal_msleep(160);
401
402 ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_CLEAR);
403 if (ret < 0)
404 goto out;
405
406 ret = usbh_asix_sw_reset(asix_class, AX_SWRESET_IPRL);
407 if (ret < 0)
408 goto out;
409
410 usb_osal_msleep(200);
411
412 if (asix_class->chipcode == AX_AX88772B_CHIPCODE) {
413 ret = usbh_asix_write_cmd(asix_class, AX_QCTCTRL, 0x8000, 0x8001, NULL, 0);
414 if (ret < 0) {
415 USB_LOG_ERR("Write BQ setting failed: %d\r\n", ret);
416 goto out;
417 }
418 } else if (asix_class->chipcode == AX_AX88772A_CHIPCODE) {
419 /* Check if the PHY registers have default settings */
420 phy14h = usbh_asix_mdio_read(asix_class, asix_class->phy_addr,
421 AX88772A_PHY14H);
422 phy15h = usbh_asix_mdio_read(asix_class, asix_class->phy_addr,
423 AX88772A_PHY15H);
424 phy16h = usbh_asix_mdio_read(asix_class, asix_class->phy_addr,
425 AX88772A_PHY16H);
426
427 USB_LOG_DBG("772a_hw_reset: MR20=0x%x MR21=0x%x MR22=0x%x\r\n",
428 phy14h, phy15h, phy16h);
429
430 /* Restore PHY registers default setting if not */
431 if (phy14h != AX88772A_PHY14H_DEFAULT)
432 usbh_asix_mdio_write(asix_class, asix_class->phy_addr,
433 AX88772A_PHY14H,
434 AX88772A_PHY14H_DEFAULT);
435 if (phy15h != AX88772A_PHY15H_DEFAULT)
436 usbh_asix_mdio_write(asix_class, asix_class->phy_addr,
437 AX88772A_PHY15H,
438 AX88772A_PHY15H_DEFAULT);
439 if (phy16h != AX88772A_PHY16H_DEFAULT)
440 usbh_asix_mdio_write(asix_class, asix_class->phy_addr,
441 AX88772A_PHY16H,
442 AX88772A_PHY16H_DEFAULT);
443 }
444
445 ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_IPG0,
446 AX88772_IPG0_DEFAULT | AX88772_IPG1_DEFAULT,
447 AX88772_IPG2_DEFAULT, NULL, 0);
448 if (ret < 0) {
449 USB_LOG_ERR("Write IPG,IPG1,IPG2 failed: %d\r\n", ret);
450 goto out;
451 }
452
453 /* Rewrite MAC address */
454 ret = usbh_asix_write_cmd(asix_class, AX_CMD_WRITE_NODE_ID, 0, 0, asix_class->mac, ETH_ALEN);
455 if (ret < 0)
456 goto out;
457
458 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
459 ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL);
460 if (ret < 0)
461 goto out;
462
463 ret = usbh_asix_write_medium_mode(asix_class, AX88772_MEDIUM_DEFAULT);
464 if (ret < 0)
465 return ret;
466
467 /* Set RX_CTL to default values with 2k buffer, and enable cactus */
468 ret = usbh_asix_write_rx_ctl(asix_class, AX_DEFAULT_RX_CTL);
469 if (ret < 0)
470 goto out;
471
472 rx_ctl = usbh_asix_read_rx_ctl(asix_class);
473 USB_LOG_INFO("RX_CTL is 0x%04x after all initializations\r\n", rx_ctl);
474
475 rx_ctl = usbh_asix_read_medium_status(asix_class);
476 USB_LOG_INFO("Medium Status is 0x%04x after all initializations\r\n", rx_ctl);
477
478 return 0;
479
480 out:
481 return ret;
482 }
483
usbh_ax88772_mac_link_down(struct usbh_asix * asix_class)484 static void usbh_ax88772_mac_link_down(struct usbh_asix *asix_class)
485 {
486 usbh_asix_write_medium_mode(asix_class, 0);
487 }
488
usbh_ax88772_mac_link_up(struct usbh_asix * asix_class,int speed,int duplex,bool tx_pause,bool rx_pause)489 static void usbh_ax88772_mac_link_up(struct usbh_asix *asix_class, int speed, int duplex, bool tx_pause, bool rx_pause)
490 {
491 uint16_t m = AX_MEDIUM_AC | AX_MEDIUM_RE;
492
493 m |= duplex ? AX_MEDIUM_FD : 0;
494
495 switch (speed) {
496 case SPEED_100:
497 m |= AX_MEDIUM_PS;
498 break;
499 case SPEED_10:
500 break;
501 default:
502 return;
503 }
504
505 if (tx_pause)
506 m |= AX_MEDIUM_TFC;
507
508 if (rx_pause)
509 m |= AX_MEDIUM_RFC;
510
511 usbh_asix_write_medium_mode(asix_class, m);
512 }
513
usbh_asix_connect(struct usbh_hubport * hport,uint8_t intf)514 static int usbh_asix_connect(struct usbh_hubport *hport, uint8_t intf)
515 {
516 struct usb_endpoint_descriptor *ep_desc;
517 int ret;
518
519 struct usbh_asix *asix_class = &g_asix_class;
520
521 memset(asix_class, 0, sizeof(struct usbh_asix));
522
523 asix_class->hport = hport;
524 asix_class->intf = intf;
525
526 hport->config.intf[intf].priv = asix_class;
527
528 if ((hport->device_desc.idVendor == 0x0b95) && (hport->device_desc.idProduct == 0x772b)) {
529 asix_class->name = "ASIX AX88772B";
530 } else if ((hport->device_desc.idVendor == 0x0b95) && (hport->device_desc.idProduct == 0x7720)) {
531 asix_class->name = "ASIX AX88772";
532 } else if ((hport->device_desc.idVendor == 0x0b95) && (hport->device_desc.idProduct == 0x1780)) {
533 asix_class->name = "ASIX AX88178";
534 }
535
536 for (uint8_t i = 0; i < (ETH_ALEN >> 1); i++) {
537 ret = usbh_asix_read_cmd(asix_class, AX_CMD_READ_EEPROM,
538 0x04 + i, 0, &asix_class->mac[i * 2], 2);
539 if (ret < 0) {
540 return ret;
541 }
542 }
543
544 USB_LOG_INFO("asix MAC address %02x:%02x:%02x:%02x:%02x:%02x\r\n",
545 asix_class->mac[0],
546 asix_class->mac[1],
547 asix_class->mac[2],
548 asix_class->mac[3],
549 asix_class->mac[4],
550 asix_class->mac[5]);
551
552 ret = usbh_asix_read_phy_addr(asix_class, true);
553 if (ret < 0) {
554 USB_LOG_ERR("Failed to read phy addr: %d\r\n", ret);
555 return ret;
556 }
557 asix_class->phy_addr = ret;
558 asix_class->embd_phy = ((ret & 0x1f) == AX_EMBD_PHY_ADDR);
559
560 ret = usbh_asix_read_cmd(asix_class, AX_CMD_STATMNGSTS_REG, 0, 0, &asix_class->chipcode, 1);
561 if (ret < 0) {
562 USB_LOG_ERR("Failed to read STATMNGSTS_REG: %d\r\n", ret);
563 return ret;
564 }
565
566 asix_class->chipcode &= AX_CHIPCODE_MASK;
567 USB_LOG_INFO("asix chipcode 0x%x\r\n", asix_class->chipcode);
568
569 if (asix_class->chipcode == AX_AX88772_CHIPCODE) {
570 usbh_ax88772_hw_reset(asix_class);
571 } else {
572 usbh_ax88772a_hw_reset(asix_class);
573 }
574 for (uint8_t i = 0; i < hport->config.intf[intf].altsetting[0].intf_desc.bNumEndpoints; i++) {
575 ep_desc = &hport->config.intf[intf].altsetting[0].ep[i].ep_desc;
576
577 if (USB_GET_ENDPOINT_TYPE(ep_desc->bmAttributes) == USB_ENDPOINT_TYPE_INTERRUPT) {
578 if (ep_desc->bEndpointAddress & 0x80) {
579 USBH_EP_INIT(asix_class->intin, ep_desc);
580 } else {
581 return -USB_ERR_NOTSUPP;
582 }
583 } else {
584 if (ep_desc->bEndpointAddress & 0x80) {
585 USBH_EP_INIT(asix_class->bulkin, ep_desc);
586 } else {
587 USBH_EP_INIT(asix_class->bulkout, ep_desc);
588 }
589 }
590 }
591
592 if (asix_class->chipcode == AX_AX88772B_CHIPCODE) {
593 usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0);
594 usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0);
595
596 usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x8200);
597 usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0);
598
599 usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x3900);
600 usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0);
601
602 usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x3100);
603 usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 4);
604
605 usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 4, 0x01e1);
606 usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 1);
607
608 usbh_asix_mdio_write(asix_class, asix_class->phy_addr, 0, 0x3300);
609 usbh_asix_mdio_read(asix_class, asix_class->phy_addr, 0);
610 }
611
612 USB_LOG_INFO("Init %s done\r\n", asix_class->name);
613
614 strncpy(hport->config.intf[intf].devname, DEV_FORMAT, CONFIG_USBHOST_DEV_NAMELEN);
615
616 USB_LOG_INFO("Register ASIX Class:%s\r\n", hport->config.intf[intf].devname);
617 usbh_asix_run(asix_class);
618 return ret;
619 }
620
usbh_asix_disconnect(struct usbh_hubport * hport,uint8_t intf)621 static int usbh_asix_disconnect(struct usbh_hubport *hport, uint8_t intf)
622 {
623 int ret = 0;
624
625 struct usbh_asix *asix_class = (struct usbh_asix *)hport->config.intf[intf].priv;
626
627 if (asix_class) {
628 if (asix_class->bulkin) {
629 usbh_kill_urb(&asix_class->bulkin_urb);
630 }
631
632 if (asix_class->bulkout) {
633 usbh_kill_urb(&asix_class->bulkout_urb);
634 }
635
636 if (asix_class->intin) {
637 usbh_kill_urb(&asix_class->intin_urb);
638 }
639
640 if (hport->config.intf[intf].devname[0] != '\0') {
641 usb_osal_thread_schedule_other();
642 USB_LOG_INFO("Unregister ASIX Class:%s\r\n", hport->config.intf[intf].devname);
643 usbh_asix_stop(asix_class);
644 }
645
646 memset(asix_class, 0, sizeof(struct usbh_asix));
647 }
648
649 return ret;
650 }
651
usbh_asix_get_connect_status(struct usbh_asix * asix_class)652 int usbh_asix_get_connect_status(struct usbh_asix *asix_class)
653 {
654 int ret;
655
656 usbh_int_urb_fill(&asix_class->intin_urb, asix_class->hport, asix_class->intin, g_asix_inttx_buffer, 8, USB_OSAL_WAITING_FOREVER, NULL, NULL);
657 ret = usbh_submit_urb(&asix_class->intin_urb);
658 if (ret < 0) {
659 return ret;
660 }
661
662 if (g_asix_inttx_buffer[1] == 0x00) {
663 if (g_asix_inttx_buffer[2] & 0x01) {
664 asix_class->connect_status = true;
665 usbh_ax88772_mac_link_up(asix_class, SPEED_100, 1, 1, 1);
666 usbh_asix_set_multicast(asix_class);
667 } else {
668 asix_class->connect_status = false;
669 usbh_ax88772_mac_link_down(asix_class);
670 }
671 }
672 return 0;
673 }
674
usbh_asix_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV)675 void usbh_asix_rx_thread(CONFIG_USB_OSAL_THREAD_SET_ARGV)
676 {
677 uint32_t g_asix_rx_length;
678 int ret;
679 uint16_t len;
680 uint16_t len_crc;
681 uint32_t data_offset;
682 #if CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE <= (16 * 1024)
683 uint32_t transfer_size = CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE;
684 #else
685 uint32_t transfer_size = (16 * 1024);
686 #endif
687
688 (void)CONFIG_USB_OSAL_THREAD_GET_ARGV;
689 USB_LOG_INFO("Create asix rx thread\r\n");
690 // clang-format off
691 find_class:
692 // clang-format on
693 g_asix_class.connect_status = false;
694 if (usbh_find_class_instance("/dev/asix") == NULL) {
695 goto delete;
696 }
697
698 while (g_asix_class.connect_status == false) {
699 ret = usbh_asix_get_connect_status(&g_asix_class);
700 if (ret < 0) {
701 usb_osal_msleep(100);
702 goto find_class;
703 }
704 usb_osal_msleep(128);
705 }
706
707 g_asix_rx_length = 0;
708 while (1) {
709 usbh_bulk_urb_fill(&g_asix_class.bulkin_urb, g_asix_class.hport, g_asix_class.bulkin, &g_asix_rx_buffer[g_asix_rx_length], transfer_size, USB_OSAL_WAITING_FOREVER, NULL, NULL);
710 ret = usbh_submit_urb(&g_asix_class.bulkin_urb);
711 if (ret < 0) {
712 goto find_class;
713 }
714
715 g_asix_rx_length += g_asix_class.bulkin_urb.actual_length;
716
717 /* A transfer is complete because last packet is a short packet.
718 * Short packet is not zero, match g_asix_rx_length % USB_GET_MAXPACKETSIZE(g_asix_class.bulkin->wMaxPacketSize).
719 * Short packet is zero, check if g_asix_class.bulkin_urb.actual_length < transfer_size, for example transfer is complete with size is 1024 < 2048.
720 */
721 if (g_asix_rx_length % USB_GET_MAXPACKETSIZE(g_asix_class.bulkin->wMaxPacketSize) ||
722 (g_asix_class.bulkin_urb.actual_length < transfer_size)) {
723 USB_LOG_DBG("rxlen:%d\r\n", g_asix_rx_length);
724
725 data_offset = 0;
726 while (g_asix_rx_length > 0) {
727 len = ((uint16_t)g_asix_rx_buffer[data_offset + 0] | ((uint16_t)(g_asix_rx_buffer[data_offset + 1]) << 8)) & 0x7ff;
728 len_crc = g_asix_rx_buffer[data_offset + 2] | ((uint16_t)(g_asix_rx_buffer[data_offset + 3]) << 8);
729
730 if (len != (~len_crc & 0x7ff)) {
731 USB_LOG_ERR("rx header error\r\n");
732 g_asix_rx_length = 0;
733 continue;
734 }
735
736 uint8_t *buf = (uint8_t *)&g_asix_rx_buffer[data_offset + 4];
737 usbh_asix_eth_input(buf, len);
738 g_asix_rx_length -= (len + 4);
739 data_offset += (len + 4);
740
741 if (g_asix_rx_length < 4) {
742 g_asix_rx_length = 0;
743 }
744 }
745 } else {
746 #if CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE <= (16 * 1024)
747 if (g_asix_rx_length == CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE) {
748 #else
749 if ((g_asix_rx_length + (16 * 1024)) > CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE) {
750 #endif
751 USB_LOG_ERR("Rx packet is overflow, please reduce tcp window size or increase CONFIG_USBHOST_ASIX_ETH_MAX_RX_SIZE\r\n");
752 while (1) {
753 }
754 }
755 }
756 }
757 // clang-format off
758 delete:
759 USB_LOG_INFO("Delete asix rx thread\r\n");
760 usb_osal_thread_delete(NULL);
761 // clang-format on
762 }
763
764 uint8_t *usbh_asix_get_eth_txbuf(void)
765 {
766 return &g_asix_tx_buffer[4];
767 }
768
769 int usbh_asix_eth_output(uint32_t buflen)
770 {
771 uint16_t actual_len;
772
773 if (g_asix_class.connect_status == false) {
774 return -USB_ERR_NOTCONN;
775 }
776
777 g_asix_tx_buffer[0] = buflen & 0xff;
778 g_asix_tx_buffer[1] = (buflen >> 8) & 0xff;
779 g_asix_tx_buffer[2] = ~g_asix_tx_buffer[0];
780 g_asix_tx_buffer[3] = ~g_asix_tx_buffer[1];
781
782 if (!(buflen + 4) % USB_GET_MAXPACKETSIZE(g_asix_class.bulkout->wMaxPacketSize)) {
783 USB_LOG_DBG("txlen:%d\r\n", buflen + 8);
784 g_asix_tx_buffer[buflen + 4 + 0] = 0x00;
785 g_asix_tx_buffer[buflen + 4 + 1] = 0x00;
786 g_asix_tx_buffer[buflen + 4 + 2] = 0xff;
787 g_asix_tx_buffer[buflen + 4 + 3] = 0xff;
788 actual_len = buflen + 8;
789 } else {
790 USB_LOG_DBG("txlen:%d\r\n", buflen + 4);
791 actual_len = buflen + 4;
792 }
793
794 usbh_bulk_urb_fill(&g_asix_class.bulkout_urb, g_asix_class.hport, g_asix_class.bulkout, g_asix_tx_buffer, actual_len, USB_OSAL_WAITING_FOREVER, NULL, NULL);
795 return usbh_submit_urb(&g_asix_class.bulkout_urb);
796 }
797
798 __WEAK void usbh_asix_run(struct usbh_asix *asix_class)
799 {
800 (void)asix_class;
801 }
802
803 __WEAK void usbh_asix_stop(struct usbh_asix *asix_class)
804 {
805 (void)asix_class;
806 }
807
808 static const uint16_t asix_id_table[][2] = {
809 { 0x0B95, 0x772B },
810 { 0x0B95, 0x7720 },
811 { 0, 0 },
812 };
813
814 static const struct usbh_class_driver asix_class_driver = {
815 .driver_name = "asix",
816 .connect = usbh_asix_connect,
817 .disconnect = usbh_asix_disconnect
818 };
819
820 CLASS_INFO_DEFINE const struct usbh_class_info asix_class_info = {
821 .match_flags = USB_CLASS_MATCH_VID_PID | USB_CLASS_MATCH_INTF_CLASS,
822 .bInterfaceClass = 0xff,
823 .bInterfaceSubClass = 0x00,
824 .bInterfaceProtocol = 0x00,
825 .id_table = asix_id_table,
826 .class_driver = &asix_class_driver
827 };