1 /*
2 * Copyright (c) 2024, sakumisu
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 */
6 #include "usbd_core.h"
7 #include "usbh_core.h"
8 #include "usb_dwc2_param.h"
9
10 #ifndef CONFIG_USB_DWC2_CUSTOM_PARAM
11
12 #if __has_include("stm32f1xx_hal.h")
13 #include "stm32f1xx_hal.h"
14
15 const struct dwc2_user_params param_pa11_pa12 = {
16 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
17 .device_dma_enable = false,
18 .device_dma_desc_enable = false,
19 .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16),
20 .device_tx_fifo_size = {
21 [0] = 16, // 64 byte
22 [1] = 16, // 64 byte
23 [2] = 16, // 64 byte
24 [3] = 16, // 64 byte
25 [4] = 0,
26 [5] = 0,
27 [6] = 0,
28 [7] = 0,
29 [8] = 0,
30 [9] = 0,
31 [10] = 0,
32 [11] = 0,
33 [12] = 0,
34 [13] = 0,
35 [14] = 0,
36 [15] = 0 },
37
38 .device_gccfg = ((1 << 16) | (1 << 21)), // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS
39 .total_fifo_size = 320 // 1280 byte
40 };
41
42 const struct dwc2_user_params param_pb14_pb15 = { 0 }; // do not support
43 #if defined(HAL_HCD_MODULE_ENABLED)
44 #error "HAL_HCD_MODULE_ENABLED is not supported for STM32F1xx, please use HAL_PCD_MODULE_ENABLED"
45 #endif
46 #elif __has_include("stm32f2xx_hal.h")
47 #include "stm32f2xx_hal.h"
48
49 const struct dwc2_user_params param_pa11_pa12 = {
50 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
51 .device_dma_enable = false,
52 .device_dma_desc_enable = false,
53 .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16),
54 .device_tx_fifo_size = {
55 [0] = 16, // 64 byte
56 [1] = 16, // 64 byte
57 [2] = 16, // 64 byte
58 [3] = 16, // 64 byte
59 [4] = 0,
60 [5] = 0,
61 [6] = 0,
62 [7] = 0,
63 [8] = 0,
64 [9] = 0,
65 [10] = 0,
66 [11] = 0,
67 [12] = 0,
68 [13] = 0,
69 [14] = 0,
70 [15] = 0 },
71
72 .device_gccfg = ((1 << 16) | (1 << 21)), // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS
73 .total_fifo_size = 320 // 1280 byte
74 };
75
76 const struct dwc2_user_params param_pb14_pb15 = {
77 #ifdef CONFIG_USB_HS
78 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
79 #else
80 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
81 #endif
82 #ifdef CONFIG_USB_DWC2_DMA_ENABLE
83 .device_dma_enable = true,
84 #else
85 .device_dma_enable = false,
86 #endif
87 .device_dma_desc_enable = false,
88 .device_rx_fifo_size = (1012 - 16 - 256 - 128 - 128 - 128 - 128),
89 .device_tx_fifo_size = {
90 [0] = 16, // 64 byte
91 [1] = 256, // 1024 byte
92 [2] = 128, // 512 byte
93 [3] = 128, // 512 byte
94 [4] = 128, // 512 byte
95 [5] = 128, // 512 byte
96 [6] = 0,
97 [7] = 0,
98 [8] = 0,
99 [9] = 0,
100 [10] = 0,
101 [11] = 0,
102 [12] = 0,
103 [13] = 0,
104 [14] = 0,
105 [15] = 0 },
106
107 .host_dma_desc_enable = false,
108 .host_rx_fifo_size = 628,
109 .host_nperio_tx_fifo_size = 128, // 512 byte
110 .host_perio_tx_fifo_size = 256, // 1024 byte
111
112 #ifdef CONFIG_USB_HS
113 .device_gccfg = 0,
114 .host_gccfg = 0,
115 #else
116 .device_gccfg = ((1 << 16) | (1 << 21)), // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS hs:0
117 .host_gccfg = ((1 << 16) | (1 << 21)) // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS hs:0
118 #endif
119 };
120 #elif __has_include("stm32f4xx_hal.h")
121 #include "stm32f4xx_hal.h"
122
123 const struct dwc2_user_params param_pa11_pa12 = {
124 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
125 .device_dma_enable = false,
126 .device_dma_desc_enable = false,
127 .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16),
128 .device_tx_fifo_size = {
129 [0] = 16, // 64 byte
130 [1] = 16, // 64 byte
131 [2] = 16, // 64 byte
132 [3] = 16, // 64 byte
133 [4] = 0,
134 [5] = 0,
135 [6] = 0,
136 [7] = 0,
137 [8] = 0,
138 [9] = 0,
139 [10] = 0,
140 [11] = 0,
141 [12] = 0,
142 [13] = 0,
143 [14] = 0,
144 [15] = 0 },
145
146 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || \
147 defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || \
148 defined(STM32F423xx)
149 .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN
150 .b_session_valid_override = true,
151 #else
152 .device_gccfg = ((1 << 16) | (1 << 21)), // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS
153 #endif
154 .total_fifo_size = 320 // 1280 byte
155 };
156
157 const struct dwc2_user_params param_pb14_pb15 = {
158 #ifdef CONFIG_USB_HS
159 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
160 #else
161 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
162 #endif
163 #ifdef CONFIG_USB_DWC2_DMA_ENABLE
164 .device_dma_enable = true,
165 #else
166 .device_dma_enable = false,
167 #endif
168 .device_dma_desc_enable = false,
169 .device_rx_fifo_size = (1006 - 16 - 256 - 128 - 128 - 128 - 128), // 1006/1012
170 .device_tx_fifo_size = {
171 [0] = 16, // 64 byte
172 [1] = 256, // 1024 byte
173 [2] = 128, // 512 byte
174 [3] = 128, // 512 byte
175 [4] = 128, // 512 byte
176 [5] = 128, // 512 byte
177 [6] = 0,
178 [7] = 0,
179 [8] = 0,
180 [9] = 0,
181 [10] = 0,
182 [11] = 0,
183 [12] = 0,
184 [13] = 0,
185 [14] = 0,
186 [15] = 0 },
187
188 .host_dma_desc_enable = false,
189 .host_rx_fifo_size = 622,
190 .host_nperio_tx_fifo_size = 128, // 512 byte
191 .host_perio_tx_fifo_size = 256, // 1024 byte
192 #ifdef CONFIG_USB_HS
193 .device_gccfg = 0,
194 .host_gccfg = 0,
195 #else
196 #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || \
197 defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || \
198 defined(STM32F423xx)
199 .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN
200 .host_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN
201 .b_session_valid_override = true,
202 #else
203 .device_gccfg = ((1 << 16) | (1 << 21)), // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS hs:0
204 .host_gccfg = ((1 << 16) | (1 << 21)) // fs: USB_OTG_GCCFG_PWRDWN | USB_OTG_GCCFG_NOVBUSSENS hs:0
205 #endif
206 #endif
207 };
208 #elif __has_include("stm32f7xx_hal.h")
209 #include "stm32f7xx_hal.h"
210
211 const struct dwc2_user_params param_pa11_pa12 = {
212 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
213 .device_dma_enable = false,
214 .device_dma_desc_enable = false,
215 .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16),
216 .device_tx_fifo_size = {
217 [0] = 16, // 64 byte
218 [1] = 16, // 64 byte
219 [2] = 16, // 64 byte
220 [3] = 16, // 64 byte
221 [4] = 0,
222 [5] = 0,
223 [6] = 0,
224 [7] = 0,
225 [8] = 0,
226 [9] = 0,
227 [10] = 0,
228 [11] = 0,
229 [12] = 0,
230 [13] = 0,
231 [14] = 0,
232 [15] = 0 },
233
234 .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN
235 .host_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN
236
237 .b_session_valid_override = true,
238 .total_fifo_size = 320 // 1280 byte
239 };
240
241 const struct dwc2_user_params param_pb14_pb15 = {
242 #if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx)
243 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
244 #else
245 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
246 #endif
247 #ifdef CONFIG_USB_DWC2_DMA_ENABLE
248 .device_dma_enable = true,
249 #else
250 .device_dma_enable = false,
251 #endif
252 .device_dma_desc_enable = false,
253 .device_rx_fifo_size = (1006 - 16 - 256 - 128 - 128 - 128 - 128),
254 .device_tx_fifo_size = {
255 [0] = 16, // 64 byte
256 [1] = 256, // 1024 byte
257 [2] = 128, // 512 byte
258 [3] = 128, // 512 byte
259 [4] = 128, // 512 byte
260 [5] = 128, // 512 byte
261 [6] = 0,
262 [7] = 0,
263 [8] = 0,
264 [9] = 0,
265 [10] = 0,
266 [11] = 0,
267 [12] = 0,
268 [13] = 0,
269 [14] = 0,
270 [15] = 0 },
271
272 .host_dma_desc_enable = false,
273 .host_rx_fifo_size = 622,
274 .host_nperio_tx_fifo_size = 128, // 512 byte
275 .host_perio_tx_fifo_size = 256, // 1024 byte
276 #if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx)
277 .device_gccfg = (1 << 23), // USB_OTG_GCCFG_PHYHSEN
278 .host_gccfg = (1 << 23), // USB_OTG_GCCFG_PHYHSEN
279 #else
280 #ifdef CONFIG_USB_HS
281 .device_gccfg = 0,
282 .host_gccfg = 0,
283 #else
284 .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0
285 .host_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0
286 #endif
287 #endif
288 .b_session_valid_override = true
289 };
290 #elif __has_include("stm32h7xx_hal.h")
291 #include "stm32h7xx_hal.h"
292
293 const struct dwc2_user_params param_pa11_pa12 = {
294 .phy_type = DWC2_PHY_TYPE_PARAM_FS, // DWC2_PHY_TYPE_PARAM_UTMI
295 #ifdef CONFIG_USB_DWC2_DMA_ENABLE
296 .device_dma_enable = true,
297 #else
298 .device_dma_enable = false,
299 #endif
300 .device_dma_desc_enable = false,
301 .device_rx_fifo_size = (952 - 16 - 256 - 128 - 128 - 128 - 128),
302 .device_tx_fifo_size = {
303 [0] = 16, // 64 byte
304 [1] = 256, // 1024 byte
305 [2] = 128, // 512 byte
306 [3] = 128, // 512 byte
307 [4] = 128, // 512 byte
308 [5] = 128, // 512 byte
309 [6] = 0,
310 [7] = 0,
311 [8] = 0,
312 [9] = 0,
313 [10] = 0,
314 [11] = 0,
315 [12] = 0,
316 [13] = 0,
317 [14] = 0,
318 [15] = 0 },
319
320 .host_dma_desc_enable = false,
321 .host_rx_fifo_size = 568,
322 .host_nperio_tx_fifo_size = 128, // 512 byte
323 .host_perio_tx_fifo_size = 256, // 1024 byte
324
325 .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0
326 .host_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0
327
328 .b_session_valid_override = true
329 };
330
331 const struct dwc2_user_params param_pb14_pb15 = {
332 #ifdef CONFIG_USB_HS
333 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
334 #else
335 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
336 #endif
337 #ifdef CONFIG_USB_DWC2_DMA_ENABLE
338 .device_dma_enable = true,
339 #else
340 .device_dma_enable = false,
341 #endif
342 .device_dma_desc_enable = false,
343 .device_rx_fifo_size = (952 - 16 - 256 - 128 - 128 - 128 - 128),
344 .device_tx_fifo_size = {
345 [0] = 16, // 64 byte
346 [1] = 256, // 1024 byte
347 [2] = 128, // 512 byte
348 [3] = 128, // 512 byte
349 [4] = 128, // 512 byte
350 [5] = 128, // 512 byte
351 [6] = 0,
352 [7] = 0,
353 [8] = 0,
354 [9] = 0,
355 [10] = 0,
356 [11] = 0,
357 [12] = 0,
358 [13] = 0,
359 [14] = 0,
360 [15] = 0 },
361
362 .host_dma_desc_enable = false,
363 .host_rx_fifo_size = 568,
364 .host_nperio_tx_fifo_size = 128, // 512 byte
365 .host_perio_tx_fifo_size = 256, // 1024 byte
366
367 #ifdef CONFIG_USB_HS
368 .device_gccfg = 0,
369 .host_gccfg = 0,
370 #else
371 .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0
372 .host_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN hs:0
373 #endif
374 .b_session_valid_override = true
375 };
376 #elif __has_include("stm32h7rsxx_hal.h")
377 #include "stm32h7rsxx_hal.h"
378
379 const struct dwc2_user_params param_pa11_pa12 = {
380 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
381 .device_dma_enable = false,
382 .device_dma_desc_enable = false,
383 .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16),
384 .device_tx_fifo_size = {
385 [0] = 16, // 64 byte
386 [1] = 16, // 64 byte
387 [2] = 16, // 64 byte
388 [3] = 16, // 64 byte
389 [4] = 0,
390 [5] = 0,
391 [6] = 0,
392 [7] = 0,
393 [8] = 0,
394 [9] = 0,
395 [10] = 0,
396 [11] = 0,
397 [12] = 0,
398 [13] = 0,
399 [14] = 0,
400 [15] = 0 },
401
402 .device_gccfg = (1 << 16), // fs: USB_OTG_GCCFG_PWRDWN
403 .b_session_valid_override = true,
404 .total_fifo_size = 320 // 1280 byte
405 };
406
407 const struct dwc2_user_params param_pb14_pb15 = {
408 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
409 #ifdef CONFIG_USB_DWC2_DMA_ENABLE
410 .device_dma_enable = true,
411 #else
412 .device_dma_enable = false,
413 #endif
414 .device_dma_desc_enable = false,
415 .device_rx_fifo_size = (952 - 16 - 256 - 128 - 128 - 128 - 128),
416 .device_tx_fifo_size = {
417 [0] = 16, // 64 byte
418 [1] = 256, // 1024 byte
419 [2] = 128, // 512 byte
420 [3] = 128, // 512 byte
421 [4] = 128, // 512 byte
422 [5] = 128, // 512 byte
423 [6] = 0,
424 [7] = 0,
425 [8] = 0,
426 [9] = 0,
427 [10] = 0,
428 [11] = 0,
429 [12] = 0,
430 [13] = 0,
431 [14] = 0,
432 [15] = 0 },
433
434 .host_dma_desc_enable = false,
435 .host_rx_fifo_size = 568,
436 .host_nperio_tx_fifo_size = 128, // 512 byte
437 .host_perio_tx_fifo_size = 256, // 1024 byte
438
439 .device_gccfg = ((1 << 23) | (1 << 24)), // hs: USB_OTG_GCCFG_VBVALEXTOEN | USB_OTG_GCCFG_VBVALOVAL
440 .host_gccfg = (1 << 25) // hs: USB_OTG_GCCFG_PULLDOWNEN
441 };
442 #elif __has_include("stm32l4xx_hal.h")
443 #include "stm32l4xx_hal.h"
444
445 const struct dwc2_user_params param_pa11_pa12 = {
446 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
447 .device_dma_enable = false,
448 .device_dma_desc_enable = false,
449 .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16),
450 .device_tx_fifo_size = {
451 [0] = 16, // 64 byte
452 [1] = 16, // 64 byte
453 [2] = 16, // 64 byte
454 [3] = 16, // 64 byte
455 [4] = 0,
456 [5] = 0,
457 [6] = 0,
458 [7] = 0,
459 [8] = 0,
460 [9] = 0,
461 [10] = 0,
462 [11] = 0,
463 [12] = 0,
464 [13] = 0,
465 [14] = 0,
466 [15] = 0 },
467
468 .device_gccfg = (1 << 16),
469 .b_session_valid_override = true,
470 .total_fifo_size = 320 // 1280 byte
471 };
472
473 const struct dwc2_user_params param_pb14_pb15 = { 0 }; // do not support
474 #if defined(HAL_HCD_MODULE_ENABLED)
475 #error "HAL_HCD_MODULE_ENABLED is not supported for STM32L4xx, please use HAL_PCD_MODULE_ENABLED"
476 #endif
477 #elif __has_include("stm32u5xx_hal.h")
478 #include "stm32u5xx_hal.h"
479
480 const struct dwc2_user_params param_pa11_pa12 = {
481 .phy_type = DWC2_PHY_TYPE_PARAM_FS,
482 .device_dma_enable = false,
483 .device_dma_desc_enable = false,
484 .device_rx_fifo_size = (320 - 16 - 16 - 16 - 16),
485 .device_tx_fifo_size = {
486 [0] = 16, // 64 byte
487 [1] = 16, // 64 byte
488 [2] = 16, // 64 byte
489 [3] = 16, // 64 byte
490 [4] = 0,
491 [5] = 0,
492 [6] = 0,
493 [7] = 0,
494 [8] = 0,
495 [9] = 0,
496 [10] = 0,
497 [11] = 0,
498 [12] = 0,
499 [13] = 0,
500 [14] = 0,
501 [15] = 0 },
502
503 .device_gccfg = (1 << 16),
504 .b_session_valid_override = true,
505 .total_fifo_size = 320 // 1280 byte
506 };
507
508 #if defined(STM32U595xx) || defined(STM32U5A5xx) || defined(STM32U599xx) || defined(STM32U5A9xx) || \
509 defined(STM32U5F7xx) || defined(STM32U5G7xx) || defined(STM32U5F9xx) || defined(STM32U5G9xx)
510 const struct dwc2_user_params param_pb14_pb15 = {
511 .phy_type = DWC2_PHY_TYPE_PARAM_UTMI,
512 #ifdef CONFIG_USB_DWC2_DMA_ENABLE
513 .device_dma_enable = true,
514 #else
515 .device_dma_enable = false,
516 #endif
517 .device_dma_desc_enable = false,
518 .device_rx_fifo_size = (952 - 16 - 256 - 128 - 128 - 128 - 128),
519 .device_tx_fifo_size = {
520 [0] = 16, // 64 byte
521 [1] = 256, // 1024 byte
522 [2] = 128, // 512 byte
523 [3] = 128, // 512 byte
524 [4] = 128, // 512 byte
525 [5] = 128, // 512 byte
526 [6] = 0,
527 [7] = 0,
528 [8] = 0,
529 [9] = 0,
530 [10] = 0,
531 [11] = 0,
532 [12] = 0,
533 [13] = 0,
534 [14] = 0,
535 [15] = 0 },
536
537 .host_dma_desc_enable = false,
538 .host_rx_fifo_size = 568,
539 .host_nperio_tx_fifo_size = 128, // 512 byte
540 .host_perio_tx_fifo_size = 256, // 1024 byte
541
542 .device_gccfg = ((1 << 23) | (1 << 24)), // hs: USB_OTG_GCCFG_VBVALEXTOEN | USB_OTG_GCCFG_VBVALOVAL
543 .host_gccfg = (1 << 25) // hs: USB_OTG_GCCFG_PULLDOWNEN
544 };
545 #else
546 const struct dwc2_user_params param_pb14_pb15 = { 0 }; // do not support
547 #endif
548 #endif
549
550 #endif // CONFIG_USB_DWC2_CUSTOM_PARAM
551
552 #if !defined(HAL_HCD_MODULE_ENABLED) && !defined(HAL_PCD_MODULE_ENABLED)
553 #error please define HAL_HCD_MODULE_ENABLED or HAL_PCD_MODULE_ENABLED in stm32xxx_hal_conf.h
554 #endif
555
556 typedef void (*usb_dwc2_irq)(uint8_t busid);
557
558 struct dwc2_instance {
559 USB_OTG_GlobalTypeDef *Instance;
560 };
561
562 static usb_dwc2_irq g_usb_dwc2_irq[2];
563 static uint8_t g_usb_dwc2_busid[2] = { 0, 0 };
564 static struct dwc2_instance g_dwc2_instance;
565
566 #if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx)
567 /**
568 * @brief Enables control of a High Speed USB PHY
569 * Init the low level hardware : GPIO, CLOCK, NVIC...
570 * @param USBx Selected device
571 * @retval HAL status
572 */
usb_hsphy_init(uint32_t hse_value)573 static int usb_hsphy_init(uint32_t hse_value)
574 {
575 __IO uint32_t count = 0U;
576
577 /* Enable LDO */
578 USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
579
580 /* wait for LDO Ready */
581 while ((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == 0U) {
582 count++;
583
584 if (count > 200000U) {
585 return -1;
586 }
587 }
588
589 /* Controls PHY frequency operation selection */
590 if (hse_value == 12000000U) /* HSE = 12MHz */
591 {
592 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x0U << 1);
593 } else if (hse_value == 12500000U) /* HSE = 12.5MHz */
594 {
595 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x2U << 1);
596 } else if (hse_value == 16000000U) /* HSE = 16MHz */
597 {
598 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x3U << 1);
599 } else if (hse_value == 24000000U) /* HSE = 24MHz */
600 {
601 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x4U << 1);
602 } else if (hse_value == 25000000U) /* HSE = 25MHz */
603 {
604 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x5U << 1);
605 } else if (hse_value == 32000000U) /* HSE = 32MHz */
606 {
607 USB_HS_PHYC->USB_HS_PHYC_PLL = (0x7U << 1);
608 } else {
609 /* ... */
610 }
611
612 /* Control the tuning interface of the High Speed PHY */
613 USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE;
614
615 /* Enable PLL internal PHY */
616 USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
617
618 /* 2ms Delay required to get internal phy clock stable */
619 HAL_Delay(2U);
620
621 return 0;
622 }
623 #endif
624
625 #ifdef HAL_PCD_MODULE_ENABLED
usb_dc_low_level_init(uint8_t busid)626 void usb_dc_low_level_init(uint8_t busid)
627 {
628 if (g_usbdev_bus[busid].reg_base == 0x40040000UL) { // USB_OTG_HS_PERIPH_BASE
629 g_usb_dwc2_busid[1] = busid;
630 g_usb_dwc2_irq[1] = USBD_IRQHandler;
631 } else {
632 g_usb_dwc2_busid[0] = busid;
633 g_usb_dwc2_irq[0] = USBD_IRQHandler;
634 }
635
636 g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)g_usbdev_bus[busid].reg_base;
637 HAL_PCD_MspInit((PCD_HandleTypeDef *)&g_dwc2_instance);
638
639 #if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx)
640 usb_hsphy_init(25000000U);
641 #endif
642 }
643
usb_dc_low_level_deinit(uint8_t busid)644 void usb_dc_low_level_deinit(uint8_t busid)
645 {
646 if (g_usbdev_bus[busid].reg_base == 0x40040000UL) { // USB_OTG_HS_PERIPH_BASE
647 g_usb_dwc2_busid[1] = 0;
648 g_usb_dwc2_irq[1] = NULL;
649 } else {
650 g_usb_dwc2_busid[0] = 0;
651 g_usb_dwc2_irq[0] = NULL;
652 }
653
654 g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)g_usbdev_bus[busid].reg_base;
655 HAL_PCD_MspDeInit((PCD_HandleTypeDef *)&g_dwc2_instance);
656 }
657 #endif
658
659 #ifdef HAL_HCD_MODULE_ENABLED
usb_hc_low_level_init(struct usbh_bus * bus)660 void usb_hc_low_level_init(struct usbh_bus *bus)
661 {
662 if (bus->hcd.reg_base == 0x40040000UL) { // USB_OTG_HS_PERIPH_BASE
663 g_usb_dwc2_busid[1] = bus->hcd.hcd_id;
664 g_usb_dwc2_irq[1] = USBH_IRQHandler;
665 } else {
666 g_usb_dwc2_busid[0] = bus->hcd.hcd_id;
667 g_usb_dwc2_irq[0] = USBH_IRQHandler;
668 }
669
670 g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)bus->hcd.reg_base;
671 HAL_HCD_MspInit((HCD_HandleTypeDef *)&g_dwc2_instance);
672
673 #if defined(STM32F722xx) || defined(STM32F723xx) || defined(STM32F730xx) || defined(STM32F732xx) || defined(STM32F733xx)
674 usb_hsphy_init(25000000U);
675 #endif
676 }
677
usb_hc_low_level_deinit(struct usbh_bus * bus)678 void usb_hc_low_level_deinit(struct usbh_bus *bus)
679 {
680 if (bus->hcd.reg_base == 0x40040000UL) { // USB_OTG_HS_PERIPH_BASE
681 g_usb_dwc2_busid[1] = 0;
682 g_usb_dwc2_irq[1] = NULL;
683 } else {
684 g_usb_dwc2_busid[0] = 0;
685 g_usb_dwc2_irq[0] = NULL;
686 }
687
688 g_dwc2_instance.Instance = (USB_OTG_GlobalTypeDef *)bus->hcd.reg_base;
689 HAL_HCD_MspDeInit((HCD_HandleTypeDef *)&g_dwc2_instance);
690 }
691 #endif
692
693 #ifndef CONFIG_USB_DWC2_CUSTOM_PARAM
dwc2_get_user_params(uint32_t reg_base,struct dwc2_user_params * params)694 void dwc2_get_user_params(uint32_t reg_base, struct dwc2_user_params *params)
695 {
696 if (reg_base == 0x40040000UL) { // USB_OTG_HS_PERIPH_BASE
697 memcpy(params, ¶m_pb14_pb15, sizeof(struct dwc2_user_params));
698 } else {
699 memcpy(params, ¶m_pa11_pa12, sizeof(struct dwc2_user_params));
700 }
701 #ifdef CONFIG_USB_DWC2_CUSTOM_FIFO
702 struct usb_dwc2_user_fifo_config s_dwc2_fifo_config;
703
704 dwc2_get_user_fifo_config(reg_base, &s_dwc2_fifo_config);
705
706 params->device_rx_fifo_size = s_dwc2_fifo_config.device_rx_fifo_size;
707 for (uint8_t i = 0; i < MAX_EPS_CHANNELS; i++)
708 {
709 params->device_tx_fifo_size[i] = s_dwc2_fifo_config.device_tx_fifo_size[i];
710 }
711 #endif
712 }
713 #endif
714
715 extern uint32_t SystemCoreClock;
716
usbd_dwc2_delay_ms(uint8_t ms)717 void usbd_dwc2_delay_ms(uint8_t ms)
718 {
719 uint32_t count = SystemCoreClock / 1000 * ms;
720 while (count--) {
721 __asm volatile("nop");
722 }
723 }
724
OTG_FS_IRQHandler(void)725 void OTG_FS_IRQHandler(void)
726 {
727 g_usb_dwc2_irq[0](g_usb_dwc2_busid[0]);
728 }
729
OTG_HS_IRQHandler(void)730 void OTG_HS_IRQHandler(void)
731 {
732 g_usb_dwc2_irq[1](g_usb_dwc2_busid[1]);
733 }
734
735 #ifdef CONFIG_USB_DCACHE_ENABLE
usb_dcache_clean(uintptr_t addr,size_t size)736 void usb_dcache_clean(uintptr_t addr, size_t size)
737 {
738 SCB_CleanDCache_by_Addr((void *)addr, size);
739 }
740
usb_dcache_invalidate(uintptr_t addr,size_t size)741 void usb_dcache_invalidate(uintptr_t addr, size_t size)
742 {
743 SCB_InvalidateDCache_by_Addr((void *)addr, size);
744 }
745
usb_dcache_flush(uintptr_t addr,size_t size)746 void usb_dcache_flush(uintptr_t addr, size_t size)
747 {
748 SCB_CleanInvalidateDCache_by_Addr((void *)addr, size);
749 }
750 #endif