1 /* 2 * Copyright (c) 2006-2020, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2011-09-15 Bernard first version 9 */ 10 11 #ifndef __ARMV8_H__ 12 #define __ARMV8_H__ 13 14 #include <rtconfig.h> 15 16 #ifdef ARCH_USING_HW_THREAD_SELF 17 #define ARM64_THREAD_REG tpidr_el1 18 #endif /* ARCH_USING_HW_THREAD_SELF */ 19 20 #ifdef __ASSEMBLY__ 21 22 /********************* 23 * CONTEXT_OFFSET * 24 *********************/ 25 26 #define CONTEXT_OFFSET_ELR_EL1 0x0 27 #define CONTEXT_OFFSET_SPSR_EL1 0x8 28 #define CONTEXT_OFFSET_SP_EL0 0x10 29 #define CONTEXT_OFFSET_X30 0x18 30 #define CONTEXT_OFFSET_FPCR 0x20 31 #define CONTEXT_OFFSET_FPSR 0x28 32 #define CONTEXT_OFFSET_X28 0x30 33 #define CONTEXT_OFFSET_X29 0x38 34 #define CONTEXT_OFFSET_X26 0x40 35 #define CONTEXT_OFFSET_X27 0x48 36 #define CONTEXT_OFFSET_X24 0x50 37 #define CONTEXT_OFFSET_X25 0x58 38 #define CONTEXT_OFFSET_X22 0x60 39 #define CONTEXT_OFFSET_X23 0x68 40 #define CONTEXT_OFFSET_X20 0x70 41 #define CONTEXT_OFFSET_X21 0x78 42 #define CONTEXT_OFFSET_X18 0x80 43 #define CONTEXT_OFFSET_X19 0x88 44 #define CONTEXT_OFFSET_X16 0x90 45 #define CONTEXT_OFFSET_X17 0x98 46 #define CONTEXT_OFFSET_X14 0xa0 47 #define CONTEXT_OFFSET_X15 0xa8 48 #define CONTEXT_OFFSET_X12 0xb0 49 #define CONTEXT_OFFSET_X13 0xb8 50 #define CONTEXT_OFFSET_X10 0xc0 51 #define CONTEXT_OFFSET_X11 0xc8 52 #define CONTEXT_OFFSET_X8 0xd0 53 #define CONTEXT_OFFSET_X9 0xd8 54 #define CONTEXT_OFFSET_X6 0xe0 55 #define CONTEXT_OFFSET_X7 0xe8 56 #define CONTEXT_OFFSET_X4 0xf0 57 #define CONTEXT_OFFSET_X5 0xf8 58 #define CONTEXT_OFFSET_X2 0x100 59 #define CONTEXT_OFFSET_X3 0x108 60 #define CONTEXT_OFFSET_X0 0x110 61 #define CONTEXT_OFFSET_X1 0x118 62 63 #define CONTEXT_OFFSET_Q31 0x120 64 #define CONTEXT_OFFSET_Q30 0x130 65 #define CONTEXT_OFFSET_Q29 0x140 66 #define CONTEXT_OFFSET_Q28 0x150 67 #define CONTEXT_OFFSET_Q27 0x160 68 #define CONTEXT_OFFSET_Q26 0x170 69 #define CONTEXT_OFFSET_Q25 0x180 70 #define CONTEXT_OFFSET_Q24 0x190 71 #define CONTEXT_OFFSET_Q23 0x1a0 72 #define CONTEXT_OFFSET_Q22 0x1b0 73 #define CONTEXT_OFFSET_Q21 0x1c0 74 #define CONTEXT_OFFSET_Q20 0x1d0 75 #define CONTEXT_OFFSET_Q19 0x1e0 76 #define CONTEXT_OFFSET_Q18 0x1f0 77 #define CONTEXT_OFFSET_Q17 0x200 78 #define CONTEXT_OFFSET_Q16 0x210 79 #define CONTEXT_OFFSET_Q15 0x220 80 #define CONTEXT_OFFSET_Q14 0x230 81 #define CONTEXT_OFFSET_Q13 0x240 82 #define CONTEXT_OFFSET_Q12 0x250 83 #define CONTEXT_OFFSET_Q11 0x260 84 #define CONTEXT_OFFSET_Q10 0x270 85 #define CONTEXT_OFFSET_Q9 0x280 86 #define CONTEXT_OFFSET_Q8 0x290 87 #define CONTEXT_OFFSET_Q7 0x2a0 88 #define CONTEXT_OFFSET_Q6 0x2b0 89 #define CONTEXT_OFFSET_Q5 0x2c0 90 #define CONTEXT_OFFSET_Q4 0x2d0 91 #define CONTEXT_OFFSET_Q3 0x2e0 92 #define CONTEXT_OFFSET_Q2 0x2f0 93 #define CONTEXT_OFFSET_Q1 0x300 94 #define CONTEXT_OFFSET_Q0 0x310 95 96 #define CONTEXT_FPU_SIZE (32 * 16) 97 #define CONTEXT_SIZE (0x120 + CONTEXT_FPU_SIZE) 98 99 #else /* !__ASSEMBLY__ */ 100 101 #include <rttypes.h> 102 103 typedef struct { rt_uint64_t value[2]; } rt_uint128_t; 104 105 /* the exception stack without VFP registers */ 106 struct rt_hw_exp_stack 107 { 108 rt_uint64_t pc; 109 rt_uint64_t cpsr; 110 rt_uint64_t sp_el0; 111 rt_uint64_t x30; 112 rt_uint64_t fpcr; 113 rt_uint64_t fpsr; 114 rt_uint64_t x28; 115 rt_uint64_t x29; 116 rt_uint64_t x26; 117 rt_uint64_t x27; 118 rt_uint64_t x24; 119 rt_uint64_t x25; 120 rt_uint64_t x22; 121 rt_uint64_t x23; 122 rt_uint64_t x20; 123 rt_uint64_t x21; 124 rt_uint64_t x18; 125 rt_uint64_t x19; 126 rt_uint64_t x16; 127 rt_uint64_t x17; 128 rt_uint64_t x14; 129 rt_uint64_t x15; 130 rt_uint64_t x12; 131 rt_uint64_t x13; 132 rt_uint64_t x10; 133 rt_uint64_t x11; 134 rt_uint64_t x8; 135 rt_uint64_t x9; 136 rt_uint64_t x6; 137 rt_uint64_t x7; 138 rt_uint64_t x4; 139 rt_uint64_t x5; 140 rt_uint64_t x2; 141 rt_uint64_t x3; 142 rt_uint64_t x0; 143 rt_uint64_t x1; 144 145 rt_uint128_t fpu[32]; 146 }; 147 148 void rt_hw_show_register(struct rt_hw_exp_stack *regs); 149 150 #define SP_ELx ((unsigned long)0x01) 151 #define SP_EL0 ((unsigned long)0x00) 152 #define PSTATE_EL1 ((unsigned long)0x04) 153 #define PSTATE_EL2 ((unsigned long)0x08) 154 #define PSTATE_EL3 ((unsigned long)0x0c) 155 156 rt_ubase_t rt_hw_get_current_el(void); 157 void rt_hw_set_elx_env(void); 158 void rt_hw_set_current_vbar(rt_ubase_t addr); 159 160 /* ESR:generic */ 161 #define ARM64_ABORT_WNR(esr) ((esr) & 0x40) 162 #define ARM64_ESR_EXTRACT_EC(esr) ((((esr) >> 26) & 0x3fU)) 163 #define ARM64_ESR_EXTRACT_FSC(esr) ((esr) & 0x3f) 164 165 /* ESR:EC */ 166 #define ARM64_EC_INST_ABORT_FROM_LO_EXCEPTION (0b100000) 167 #define ARM64_EC_INST_ABORT_WITHOUT_A_CHANGE (0b100001) 168 #define ARM64_EC_DATA_ABORT_FROM_LO_EXCEPTION (0b100100) 169 #define ARM64_EC_DATA_ABORT_WITHOUT_A_CHANGE (0b100101) 170 171 /* ESR:FSC */ 172 #define ARM64_FSC_TRANSLATION_FAULT_LEVEL_0 (0b000100) 173 #define ARM64_FSC_TRANSLATION_FAULT_LEVEL_1 (0b000101) 174 #define ARM64_FSC_TRANSLATION_FAULT_LEVEL_2 (0b000110) 175 #define ARM64_FSC_TRANSLATION_FAULT_LEVEL_3 (0b000111) 176 #define ARM64_FSC_PERMISSION_FAULT_LEVEL_0 (0b001100) 177 #define ARM64_FSC_PERMISSION_FAULT_LEVEL_1 (0b001101) 178 #define ARM64_FSC_PERMISSION_FAULT_LEVEL_2 (0b001110) 179 #define ARM64_FSC_PERMISSION_FAULT_LEVEL_3 (0b001111) 180 #define ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_0 (0b001000) 181 #define ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_1 (0b001001) 182 #define ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_2 (0b001010) 183 #define ARM64_FSC_ACCESS_FLAG_FAULT_LEVEL_3 (0b001011) 184 185 #endif /* __ASSEMBLY__ */ 186 187 #endif 188