1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2006-08-23 Bernard first version 9 */ 10 11 #ifndef __AT91SAM7S_H__ 12 #define __AT91SAM7S_H__ 13 14 #ifdef __cplusplus 15 extern "C" { 16 #endif 17 18 #define AT91_REG *(volatile unsigned int *) /* Hardware register definition */ 19 20 /* ========== Register definition for TC0 peripheral ========== */ 21 #define AT91C_TC0_SR (AT91_REG(0xFFFA0020)) /* TC0 Status Register */ 22 #define AT91C_TC0_RC (AT91_REG(0xFFFA001C)) /* TC0 Register C */ 23 #define AT91C_TC0_RB (AT91_REG(0xFFFA0018)) /* TC0 Register B */ 24 #define AT91C_TC0_CCR (AT91_REG(0xFFFA0000)) /* TC0 Channel Control Register */ 25 #define AT91C_TC0_CMR (AT91_REG(0xFFFA0004)) /* TC0 Channel Mode Register (Capture Mode / Waveform Mode) */ 26 #define AT91C_TC0_IER (AT91_REG(0xFFFA0024)) /* TC0 Interrupt Enable Register */ 27 #define AT91C_TC0_RA (AT91_REG(0xFFFA0014)) /* TC0 Register A */ 28 #define AT91C_TC0_IDR (AT91_REG(0xFFFA0028)) /* TC0 Interrupt Disable Register */ 29 #define AT91C_TC0_CV (AT91_REG(0xFFFA0010)) /* TC0 Counter Value */ 30 #define AT91C_TC0_IMR (AT91_REG(0xFFFA002C)) /* TC0 Interrupt Mask Register */ 31 32 /* ========== Register definition for TC1 peripheral ========== */ 33 #define AT91C_TC1_RB (AT91_REG(0xFFFA0058)) /* TC1 Register B */ 34 #define AT91C_TC1_CCR (AT91_REG(0xFFFA0040)) /* TC1 Channel Control Register */ 35 #define AT91C_TC1_IER (AT91_REG(0xFFFA0064)) /* TC1 Interrupt Enable Register */ 36 #define AT91C_TC1_IDR (AT91_REG(0xFFFA0068)) /* TC1 Interrupt Disable Register */ 37 #define AT91C_TC1_SR (AT91_REG(0xFFFA0060)) /* TC1 Status Register */ 38 #define AT91C_TC1_CMR (AT91_REG(0xFFFA0044)) /* TC1 Channel Mode Register (Capture Mode / Waveform Mode) */ 39 #define AT91C_TC1_RA (AT91_REG(0xFFFA0054)) /* TC1 Register A */ 40 #define AT91C_TC1_RC (AT91_REG(0xFFFA005C)) /* TC1 Register C */ 41 #define AT91C_TC1_IMR (AT91_REG(0xFFFA006C)) /* TC1 Interrupt Mask Register */ 42 #define AT91C_TC1_CV (AT91_REG(0xFFFA0050)) /* TC1 Counter Value */ 43 44 /* ========== Register definition for TC2 peripheral ========== */ 45 #define AT91C_TC2_CMR (AT91_REG(0xFFFA0084)) /* TC2 Channel Mode Register (Capture Mode / Waveform Mode) */ 46 #define AT91C_TC2_CCR (AT91_REG(0xFFFA0080)) /* TC2 Channel Control Register */ 47 #define AT91C_TC2_CV (AT91_REG(0xFFFA0090)) /* TC2 Counter Value */ 48 #define AT91C_TC2_RA (AT91_REG(0xFFFA0094)) /* TC2 Register A */ 49 #define AT91C_TC2_RB (AT91_REG(0xFFFA0098)) /* TC2 Register B */ 50 #define AT91C_TC2_IDR (AT91_REG(0xFFFA00A8)) /* TC2 Interrupt Disable Register */ 51 #define AT91C_TC2_IMR (AT91_REG(0xFFFA00AC)) /* TC2 Interrupt Mask Register */ 52 #define AT91C_TC2_RC (AT91_REG(0xFFFA009C)) /* TC2 Register C */ 53 #define AT91C_TC2_IER (AT91_REG(0xFFFA00A4)) /* TC2 Interrupt Enable Register */ 54 #define AT91C_TC2_SR (AT91_REG(0xFFFA00A0)) /* TC2 Status Register */ 55 56 /* ========== Register definition for PITC peripheral ========== */ 57 #define AT91C_PITC_PIVR (AT91_REG(0xFFFFFD38)) /* PITC Period Interval Value Register */ 58 #define AT91C_PITC_PISR (AT91_REG(0xFFFFFD34)) /* PITC Period Interval Status Register */ 59 #define AT91C_PITC_PIIR (AT91_REG(0xFFFFFD3C)) /* PITC Period Interval Image Register */ 60 #define AT91C_PITC_PIMR (AT91_REG(0xFFFFFD30)) /* PITC Period Interval Mode Register */ 61 62 /* ========== Register definition for UDP peripheral ========== */ 63 #define AT91C_UDP_NUM (AT91_REG(0xFFFB0000)) /* UDP Frame Number Register */ 64 #define AT91C_UDP_STAT (AT91_REG(0xFFFB0004)) /* UDP Global State Register */ 65 #define AT91C_UDP_FADDR (AT91_REG(0xFFFB0008)) /* UDP Function Address Register */ 66 #define AT91C_UDP_IER (AT91_REG(0xFFFB0010)) /* UDP Interrupt Enable Register */ 67 #define AT91C_UDP_IDR (AT91_REG(0xFFFB0014)) /* UDP Interrupt Disable Register */ 68 #define AT91C_UDP_IMR (AT91_REG(0xFFFB0018)) /* UDP Interrupt Mask Register */ 69 #define AT91C_UDP_ISR (AT91_REG(0xFFFB001C)) /* UDP Interrupt Status Register */ 70 #define AT91C_UDP_ICR (AT91_REG(0xFFFB0020)) /* UDP Interrupt Clear Register */ 71 #define AT91C_UDP_RSTEP (AT91_REG(0xFFFB0028)) /* UDP Reset Endpoint Register */ 72 #define AT91C_UDP_CSR0 (AT91_REG(0xFFFB0030)) /* UDP Endpoint Control and Status Register */ 73 #define AT91C_UDP_CSR(n) (*(&AT91C_UDP_CSR0 + n)) 74 #define AT91C_UDP_FDR0 (AT91_REG(0xFFFB0050)) /* UDP Endpoint FIFO Data Register */ 75 #define AT91C_UDP_FDR(n) (*(&AT91C_UDP_FDR0 + n)) 76 #define AT91C_UDP_TXVC (AT91_REG(0xFFFB0074)) /* UDP Transceiver Control Register */ 77 78 /* ========== Register definition for US0 peripheral ========== */ 79 #define AT91C_US0_CR (AT91_REG(0xFFFC0000)) /* US0 Control Register */ 80 #define AT91C_US0_MR (AT91_REG(0xFFFC0004)) /* US0 Mode Register */ 81 #define AT91C_US0_IER (AT91_REG(0xFFFC0008)) /* US0 Interrupt Enable Register */ 82 #define AT91C_US0_IDR (AT91_REG(0xFFFC000C)) /* US0 Interrupt Disable Register */ 83 #define AT91C_US0_IMR (AT91_REG(0xFFFC0010)) /* US0 Interrupt Mask Register */ 84 #define AT91C_US0_CSR (AT91_REG(0xFFFC0014)) /* US0 Channel Status Register */ 85 #define AT91C_US0_RHR (AT91_REG(0xFFFC0018)) /* US0 Receiver Holding Register */ 86 #define AT91C_US0_THR (AT91_REG(0xFFFC001C)) /* US0 Transmitter Holding Register */ 87 #define AT91C_US0_BRGR (AT91_REG(0xFFFC0020)) /* US0 Baud Rate Generator Register */ 88 #define AT91C_US0_RTOR (AT91_REG(0xFFFC0024)) /* US0 Receiver Time-out Register */ 89 #define AT91C_US0_TTGR (AT91_REG(0xFFFC0028)) /* US0 Transmitter Time-guard Register */ 90 #define AT91C_US0_NER (AT91_REG(0xFFFC0044)) /* US0 Nb Errors Register */ 91 #define AT91C_US0_FIDI (AT91_REG(0xFFFC0040)) /* US0 FI_DI_Ratio Register */ 92 #define AT91C_US0_IF (AT91_REG(0xFFFC004C)) /* US0 IRDA_FILTER Register */ 93 94 /* ========== Register definition for AIC peripheral ========== */ 95 #define AT91C_AIC_SMR0 (AT91_REG(0xFFFFF000)) /* AIC Source Mode Register */ 96 #define AT91C_AIC_SMR(n) (*(&AT91C_AIC_SMR0 + n)) 97 #define AT91C_AIC_SVR0 (AT91_REG(0xFFFFF080)) /* AIC Source Vector Register */ 98 #define AT91C_AIC_SVR(n) (*(&AT91C_AIC_SVR0 + n)) 99 #define AT91C_AIC_IVR (AT91_REG(0xFFFFF100)) /* AIC Interrupt Vector Register */ 100 #define AT91C_AIC_FVR (AT91_REG(0xFFFFF104)) /* AIC FIQ Vector Register */ 101 #define AT91C_AIC_ISR (AT91_REG(0xFFFFF108)) /* AIC Interrupt Status Register */ 102 #define AT91C_AIC_IPR (AT91_REG(0xFFFFF10C)) /* AIC Interrupt Pending Register */ 103 #define AT91C_AIC_IMR (AT91_REG(0xFFFFF110)) /* AIC Interrupt Mask Register */ 104 #define AT91C_AIC_CISR (AT91_REG(0xFFFFF114)) /* AIC Core Interrupt Status Register */ 105 #define AT91C_AIC_IECR (AT91_REG(0xFFFFF120)) /* AIC Interrupt Enable Command Register */ 106 #define AT91C_AIC_IDCR (AT91_REG(0xFFFFF124)) /* AIC Interrupt Disable Command Register */ 107 #define AT91C_AIC_ICCR (AT91_REG(0xFFFFF128)) /* AIC Interrupt Clear Command Register */ 108 #define AT91C_AIC_ISCR (AT91_REG(0xFFFFF12C)) /* AIC Interrupt Set Command Register */ 109 #define AT91C_AIC_EOICR (AT91_REG(0xFFFFF130)) /* AIC End of Interrupt Command Register */ 110 #define AT91C_AIC_SPU (AT91_REG(0xFFFFF134)) /* AIC Spurious Vector Register */ 111 #define AT91C_AIC_DCR (AT91_REG(0xFFFFF138)) /* AIC Debug Control Register (Protect) */ 112 #define AT91C_AIC_FFER (AT91_REG(0xFFFFF140)) /* AIC Fast Forcing Enable Register */ 113 #define AT91C_AIC_FFDR (AT91_REG(0xFFFFF144)) /* AIC Fast Forcing Disable Register */ 114 #define AT91C_AIC_FFSR (AT91_REG(0xFFFFF148)) /* AIC Fast Forcing Status Register */ 115 116 117 /* ========== Register definition for DBGU peripheral ========== */ 118 #define AT91C_DBGU_EXID (AT91_REG(0xFFFFF244)) /* DBGU Chip ID Extension Register */ 119 #define AT91C_DBGU_BRGR (AT91_REG(0xFFFFF220)) /* DBGU Baud Rate Generator Register */ 120 #define AT91C_DBGU_IDR (AT91_REG(0xFFFFF20C)) /* DBGU Interrupt Disable Register */ 121 #define AT91C_DBGU_CSR (AT91_REG(0xFFFFF214)) /* DBGU Channel Status Register */ 122 #define AT91C_DBGU_CIDR (AT91_REG(0xFFFFF240)) /* DBGU Chip ID Register */ 123 #define AT91C_DBGU_MR (AT91_REG(0xFFFFF204)) /* DBGU Mode Register */ 124 #define AT91C_DBGU_IMR (AT91_REG(0xFFFFF210)) /* DBGU Interrupt Mask Register */ 125 #define AT91C_DBGU_CR (AT91_REG(0xFFFFF200)) /* DBGU Control Register */ 126 #define AT91C_DBGU_FNTR (AT91_REG(0xFFFFF248)) /* DBGU Force NTRST Register */ 127 #define AT91C_DBGU_THR (AT91_REG(0xFFFFF21C)) /* DBGU Transmitter Holding Register */ 128 #define AT91C_DBGU_RHR (AT91_REG(0xFFFFF218)) /* DBGU Receiver Holding Register */ 129 #define AT91C_DBGU_IER (AT91_REG(0xFFFFF208)) /* DBGU Interrupt Enable Register */ 130 131 /* ========== Register definition for PIO peripheral ========== */ 132 #define AT91C_PIO_ODR (AT91_REG(0xFFFFF414)) /* PIOA Output Disable Registerr */ 133 #define AT91C_PIO_SODR (AT91_REG(0xFFFFF430)) /* PIOA Set Output Data Register */ 134 #define AT91C_PIO_ISR (AT91_REG(0xFFFFF44C)) /* PIOA Interrupt Status Register */ 135 #define AT91C_PIO_ABSR (AT91_REG(0xFFFFF478)) /* PIOA AB Select Status Register */ 136 #define AT91C_PIO_IER (AT91_REG(0xFFFFF440)) /* PIOA Interrupt Enable Register */ 137 #define AT91C_PIO_PPUDR (AT91_REG(0xFFFFF460)) /* PIOA Pull-up Disable Register */ 138 #define AT91C_PIO_IMR (AT91_REG(0xFFFFF448)) /* PIOA Interrupt Mask Register */ 139 #define AT91C_PIO_PER (AT91_REG(0xFFFFF400)) /* PIOA PIO Enable Register */ 140 #define AT91C_PIO_IFDR (AT91_REG(0xFFFFF424)) /* PIOA Input Filter Disable Register */ 141 #define AT91C_PIO_OWDR (AT91_REG(0xFFFFF4A4)) /* PIOA Output Write Disable Register */ 142 #define AT91C_PIO_MDSR (AT91_REG(0xFFFFF458)) /* PIOA Multi-driver Status Register */ 143 #define AT91C_PIO_IDR (AT91_REG(0xFFFFF444)) /* PIOA Interrupt Disable Register */ 144 #define AT91C_PIO_ODSR (AT91_REG(0xFFFFF438)) /* PIOA Output Data Status Register */ 145 #define AT91C_PIO_PPUSR (AT91_REG(0xFFFFF468)) /* PIOA Pull-up Status Register */ 146 #define AT91C_PIO_OWSR (AT91_REG(0xFFFFF4A8)) /* PIOA Output Write Status Register */ 147 #define AT91C_PIO_BSR (AT91_REG(0xFFFFF474)) /* PIOA Select B Register */ 148 #define AT91C_PIO_OWER (AT91_REG(0xFFFFF4A0)) /* PIOA Output Write Enable Register */ 149 #define AT91C_PIO_IFER (AT91_REG(0xFFFFF420)) /* PIOA Input Filter Enable Register */ 150 #define AT91C_PIO_PDSR (AT91_REG(0xFFFFF43C)) /* PIOA Pin Data Status Register */ 151 #define AT91C_PIO_PPUER (AT91_REG(0xFFFFF464)) /* PIOA Pull-up Enable Register */ 152 #define AT91C_PIO_OSR (AT91_REG(0xFFFFF418)) /* PIOA Output Status Register */ 153 #define AT91C_PIO_ASR (AT91_REG(0xFFFFF470)) /* PIOA Select A Register */ 154 #define AT91C_PIO_MDDR (AT91_REG(0xFFFFF454)) /* PIOA Multi-driver Disable Register */ 155 #define AT91C_PIO_CODR (AT91_REG(0xFFFFF434)) /* PIOA Clear Output Data Register */ 156 #define AT91C_PIO_MDER (AT91_REG(0xFFFFF450)) /* PIOA Multi-driver Enable Register */ 157 #define AT91C_PIO_PDR (AT91_REG(0xFFFFF404)) /* PIOA PIO Disable Register */ 158 #define AT91C_PIO_IFSR (AT91_REG(0xFFFFF428)) /* PIOA Input Filter Status Register */ 159 #define AT91C_PIO_OER (AT91_REG(0xFFFFF410)) /* PIOA Output Enable Register */ 160 #define AT91C_PIO_PSR (AT91_REG(0xFFFFF408)) /* PIOA PIO Status Register */ 161 162 // ========== Register definition for PIOA peripheral ========== 163 #define AT91C_PIOA_IMR (AT91_REG(0xFFFFF448)) // (PIOA) Interrupt Mask Register 164 #define AT91C_PIOA_IER (AT91_REG(0xFFFFF440)) // (PIOA) Interrupt Enable Register 165 #define AT91C_PIOA_OWDR (AT91_REG(0xFFFFF4A4)) // (PIOA) Output Write Disable Register 166 #define AT91C_PIOA_ISR (AT91_REG(0xFFFFF44C)) // (PIOA) Interrupt Status Register 167 #define AT91C_PIOA_PPUDR (AT91_REG(0xFFFFF460)) // (PIOA) Pull-up Disable Register 168 #define AT91C_PIOA_MDSR (AT91_REG(0xFFFFF458)) // (PIOA) Multi-driver Status Register 169 #define AT91C_PIOA_MDER (AT91_REG(0xFFFFF450)) // (PIOA) Multi-driver Enable Register 170 #define AT91C_PIOA_PER (AT91_REG(0xFFFFF400)) // (PIOA) PIO Enable Register 171 #define AT91C_PIOA_PSR (AT91_REG(0xFFFFF408)) // (PIOA) PIO Status Register 172 #define AT91C_PIOA_OER (AT91_REG(0xFFFFF410)) // (PIOA) Output Enable Register 173 #define AT91C_PIOA_BSR (AT91_REG(0xFFFFF474)) // (PIOA) Select B Register 174 #define AT91C_PIOA_PPUER (AT91_REG(0xFFFFF464)) // (PIOA) Pull-up Enable Register 175 #define AT91C_PIOA_MDDR (AT91_REG(0xFFFFF454)) // (PIOA) Multi-driver Disable Register 176 #define AT91C_PIOA_PDR (AT91_REG(0xFFFFF404)) // (PIOA) PIO Disable Register 177 #define AT91C_PIOA_ODR (AT91_REG(0xFFFFF414)) // (PIOA) Output Disable Registerr 178 #define AT91C_PIOA_IFDR (AT91_REG(0xFFFFF424)) // (PIOA) Input Filter Disable Register 179 #define AT91C_PIOA_ABSR (AT91_REG(0xFFFFF478)) // (PIOA) AB Select Status Register 180 #define AT91C_PIOA_ASR (AT91_REG(0xFFFFF470)) // (PIOA) Select A Register 181 #define AT91C_PIOA_PPUSR (AT91_REG(0xFFFFF468)) // (PIOA) Pull-up Status Register 182 #define AT91C_PIOA_ODSR (AT91_REG(0xFFFFF438)) // (PIOA) Output Data Status Register 183 #define AT91C_PIOA_SODR (AT91_REG(0xFFFFF430)) // (PIOA) Set Output Data Register 184 #define AT91C_PIOA_IFSR (AT91_REG(0xFFFFF428)) // (PIOA) Input Filter Status Register 185 #define AT91C_PIOA_IFER (AT91_REG(0xFFFFF420)) // (PIOA) Input Filter Enable Register 186 #define AT91C_PIOA_OSR (AT91_REG(0xFFFFF418)) // (PIOA) Output Status Register 187 #define AT91C_PIOA_IDR (AT91_REG(0xFFFFF444)) // (PIOA) Interrupt Disable Register 188 #define AT91C_PIOA_PDSR (AT91_REG(0xFFFFF43C)) // (PIOA) Pin Data Status Register 189 #define AT91C_PIOA_CODR (AT91_REG(0xFFFFF434)) // (PIOA) Clear Output Data Register 190 #define AT91C_PIOA_OWSR (AT91_REG(0xFFFFF4A8)) // (PIOA) Output Write Status Register 191 #define AT91C_PIOA_OWER (AT91_REG(0xFFFFF4A0)) // (PIOA) Output Write Enable Register 192 // ========== Register definition for PIOB peripheral ========== 193 #define AT91C_PIOB_OWSR (AT91_REG(0xFFFFF6A8)) // (PIOB) Output Write Status Register 194 #define AT91C_PIOB_PPUSR (AT91_REG(0xFFFFF668)) // (PIOB) Pull-up Status Register 195 #define AT91C_PIOB_PPUDR (AT91_REG(0xFFFFF660)) // (PIOB) Pull-up Disable Register 196 #define AT91C_PIOB_MDSR (AT91_REG(0xFFFFF658)) // (PIOB) Multi-driver Status Register 197 #define AT91C_PIOB_MDER (AT91_REG(0xFFFFF650)) // (PIOB) Multi-driver Enable Register 198 #define AT91C_PIOB_IMR (AT91_REG(0xFFFFF648)) // (PIOB) Interrupt Mask Register 199 #define AT91C_PIOB_OSR (AT91_REG(0xFFFFF618)) // (PIOB) Output Status Register 200 #define AT91C_PIOB_OER (AT91_REG(0xFFFFF610)) // (PIOB) Output Enable Register 201 #define AT91C_PIOB_PSR (AT91_REG(0xFFFFF608)) // (PIOB) PIO Status Register 202 #define AT91C_PIOB_PER (AT91_REG(0xFFFFF600)) // (PIOB) PIO Enable Register 203 #define AT91C_PIOB_BSR (AT91_REG(0xFFFFF674)) // (PIOB) Select B Register 204 #define AT91C_PIOB_PPUER (AT91_REG(0xFFFFF664)) // (PIOB) Pull-up Enable Register 205 #define AT91C_PIOB_IFDR (AT91_REG(0xFFFFF624)) // (PIOB) Input Filter Disable Register 206 #define AT91C_PIOB_ODR (AT91_REG(0xFFFFF614)) // (PIOB) Output Disable Registerr 207 #define AT91C_PIOB_ABSR (AT91_REG(0xFFFFF678)) // (PIOB) AB Select Status Register 208 #define AT91C_PIOB_ASR (AT91_REG(0xFFFFF670)) // (PIOB) Select A Register 209 #define AT91C_PIOB_IFER (AT91_REG(0xFFFFF620)) // (PIOB) Input Filter Enable Register 210 #define AT91C_PIOB_IFSR (AT91_REG(0xFFFFF628)) // (PIOB) Input Filter Status Register 211 #define AT91C_PIOB_SODR (AT91_REG(0xFFFFF630)) // (PIOB) Set Output Data Register 212 #define AT91C_PIOB_ODSR (AT91_REG(0xFFFFF638)) // (PIOB) Output Data Status Register 213 #define AT91C_PIOB_CODR (AT91_REG(0xFFFFF634)) // (PIOB) Clear Output Data Register 214 #define AT91C_PIOB_PDSR (AT91_REG(0xFFFFF63C)) // (PIOB) Pin Data Status Register 215 #define AT91C_PIOB_OWER (AT91_REG(0xFFFFF6A0)) // (PIOB) Output Write Enable Register 216 #define AT91C_PIOB_IER (AT91_REG(0xFFFFF640)) // (PIOB) Interrupt Enable Register 217 #define AT91C_PIOB_OWDR (AT91_REG(0xFFFFF6A4)) // (PIOB) Output Write Disable Register 218 #define AT91C_PIOB_MDDR (AT91_REG(0xFFFFF654)) // (PIOB) Multi-driver Disable Register 219 #define AT91C_PIOB_ISR (AT91_REG(0xFFFFF64C)) // (PIOB) Interrupt Status Register 220 #define AT91C_PIOB_IDR (AT91_REG(0xFFFFF644)) // (PIOB) Interrupt Disable Register 221 #define AT91C_PIOB_PDR (AT91_REG(0xFFFFF604)) // (PIOB) PIO Disable Register 222 223 /* ========== Register definition for PMC peripheral ========== */ 224 #define AT91C_PMC_SCER (AT91_REG(0xFFFFFC00)) /* PMC System Clock Enable Register */ 225 #define AT91C_PMC_SCDR (AT91_REG(0xFFFFFC04)) /* PMC System Clock Disable Register */ 226 #define AT91C_PMC_SCSR (AT91_REG(0xFFFFFC08)) /* PMC System Clock Status Register */ 227 #define AT91C_PMC_PCER (AT91_REG(0xFFFFFC10)) /* PMC Peripheral Clock Enable Register */ 228 #define AT91C_PMC_PCDR (AT91_REG(0xFFFFFC14)) /* PMC Peripheral Clock Disable Register */ 229 #define AT91C_PMC_PCSR (AT91_REG(0xFFFFFC18)) /* PMC Peripheral Clock Status Register */ 230 #define AT91C_PMC_MOR (AT91_REG(0xFFFFFC20)) /* PMC Main Oscillator Register */ 231 #define AT91C_PMC_MCFR (AT91_REG(0xFFFFFC24)) /* PMC Main Clock Frequency Register */ 232 #define AT91C_PMC_PLLR (AT91_REG(0xFFFFFC2C)) /* PMC PLL Register */ 233 #define AT91C_PMC_MCKR (AT91_REG(0xFFFFFC30)) /* PMC Master Clock Register */ 234 #define AT91C_PMC_PCKR (AT91_REG(0xFFFFFC40)) /* PMC Programmable Clock Register */ 235 #define AT91C_PMC_IER (AT91_REG(0xFFFFFC60)) /* PMC Interrupt Enable Register */ 236 #define AT91C_PMC_IDR (AT91_REG(0xFFFFFC64)) /* PMC Interrupt Disable Register */ 237 #define AT91C_PMC_SR (AT91_REG(0xFFFFFC68)) /* PMC Status Register */ 238 #define AT91C_PMC_IMR (AT91_REG(0xFFFFFC6C)) /* PMC Interrupt Mask Register */ 239 240 /******************************************************************************/ 241 /* PERIPHERAL ID DEFINITIONS FOR AT91SAM7S64 */ 242 /******************************************************************************/ 243 #define AT91C_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ 244 #define AT91C_ID_SYS 1 /* System Peripheral */ 245 #define AT91C_ID_PIOA 2 /* Parallel IO Controller A */ 246 #define AT91C_ID_PIOB 3 /* Parallel IO Controller B */ 247 #define AT91C_ID_ADC 4 /* Analog-to-Digital Converter */ 248 #define AT91C_ID_SPI 5 /* Serial Peripheral Interface */ 249 #define AT91C_ID_US0 6 /* USART 0 */ 250 #define AT91C_ID_US1 7 /* USART 1 */ 251 #define AT91C_ID_SSC 8 /* Serial Synchronous Controller */ 252 #define AT91C_ID_TWI 9 /* Two-Wire Interface */ 253 #define AT91C_ID_PWMC 10 /* PWM Controller */ 254 #define AT91C_ID_UDP 11 /* USB Device Port */ 255 #define AT91C_ID_TC0 12 /* Timer Counter 0 */ 256 #define AT91C_ID_TC1 13 /* Timer Counter 1 */ 257 #define AT91C_ID_TC2 14 /* Timer Counter 2 */ 258 #define AT91C_ID_15 15 /* Reserved */ 259 #define AT91C_ID_16 16 /* Reserved */ 260 #define AT91C_ID_17 17 /* Reserved */ 261 #define AT91C_ID_18 18 /* Reserved */ 262 #define AT91C_ID_19 19 /* Reserved */ 263 #define AT91C_ID_20 20 /* Reserved */ 264 #define AT91C_ID_21 21 /* Reserved */ 265 #define AT91C_ID_22 22 /* Reserved */ 266 #define AT91C_ID_23 23 /* Reserved */ 267 #define AT91C_ID_24 24 /* Reserved */ 268 #define AT91C_ID_25 25 /* Reserved */ 269 #define AT91C_ID_26 26 /* Reserved */ 270 #define AT91C_ID_27 27 /* Reserved */ 271 #define AT91C_ID_28 28 /* Reserved */ 272 #define AT91C_ID_29 29 /* Reserved */ 273 #define AT91C_ID_IRQ0 30 /* Advanced Interrupt Controller (IRQ0) */ 274 #define AT91C_ID_IRQ1 31 /* Advanced Interrupt Controller (IRQ1) */ 275 #define AT91C_ALL_INT 0xC0007FF7 /* ALL VALID INTERRUPTS */ 276 277 /*****************************/ 278 /* CPU Mode */ 279 /*****************************/ 280 #define USERMODE 0x10 281 #define FIQMODE 0x11 282 #define IRQMODE 0x12 283 #define SVCMODE 0x13 284 #define ABORTMODE 0x17 285 #define UNDEFMODE 0x1b 286 #define MODEMASK 0x1f 287 #define NOINT 0xc0 288 289 #ifdef __cplusplus 290 } 291 #endif 292 293 #endif 294