1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2013-07-06 Bernard first version
9 * 2015-11-06 zchong support iar compiler
10 */
11
12 #include <rthw.h>
13 #include <rtthread.h>
14
15 #include "am33xx.h"
16 #include "interrupt.h"
17
18 #define AINTC_BASE AM33XX_AINTC_REGS
19
20 #define MAX_HANDLERS 128
21
22 extern volatile rt_atomic_t rt_interrupt_nest;
23
24 /* exception and interrupt handler table */
25 struct rt_irq_desc isr_table[MAX_HANDLERS];
26 rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
27 rt_uint32_t rt_thread_switch_interrupt_flag;
28
29 /**
30 * @addtogroup AM33xx
31 */
32 /*@{*/
33
rt_dump_aintc(void)34 void rt_dump_aintc(void)
35 {
36 int k;
37 rt_kprintf("active irq %d", INTC_SIR_IRQ(AINTC_BASE));
38 rt_kprintf("\n--- hw mask ---\n");
39 for (k = 0; k < 4; k++)
40 {
41 rt_kprintf("0x%08x, ", INTC_MIR(AINTC_BASE, k));
42 }
43 rt_kprintf("\n--- hw itr ---\n");
44 for (k = 0; k < 4; k++)
45 {
46 rt_kprintf("0x%08x, ", INTC_ITR(AINTC_BASE, k));
47 }
48 rt_kprintf("\n");
49 }
50
51 const unsigned int AM335X_VECTOR_BASE = 0x4030FC00;
52 extern void rt_cpu_vector_set_base(unsigned int addr);
53 #ifdef __ICCARM__
54 extern int __vector;
55 #else
56 extern int system_vectors;
57 #endif
58
rt_hw_vector_init(void)59 static void rt_hw_vector_init(void)
60 {
61 unsigned int *dest = (unsigned int *)AM335X_VECTOR_BASE;
62
63 #ifdef __ICCARM__
64 unsigned int *src = (unsigned int *)&__vector;
65 #else
66 unsigned int *src = (unsigned int *)&system_vectors;
67 #endif
68
69 rt_memcpy(dest, src, 16 * 4);
70 rt_cpu_vector_set_base(AM335X_VECTOR_BASE);
71 }
72
73 /**
74 * This function will initialize hardware interrupt
75 */
rt_hw_interrupt_init(void)76 void rt_hw_interrupt_init(void)
77 {
78 /* Reset the ARM interrupt controller */
79 INTC_SYSCONFIG(AINTC_BASE) = INTC_SYSCONFIG_SOFTRESET;
80
81 /* Wait for the reset to complete */
82 while((INTC_SYSSTATUS(AINTC_BASE)
83 & INTC_SYSSTATUS_RESETDONE) != INTC_SYSSTATUS_RESETDONE);
84
85 /* Enable any interrupt generation by setting priority threshold */
86 INTC_THRESHOLD(AINTC_BASE) = INTC_THRESHOLD_PRIORITYTHRESHOLD;
87
88 /* initialize vector table */
89 rt_hw_vector_init();
90
91 /* init exceptions table */
92 rt_memset(isr_table, 0x00, sizeof(isr_table));
93
94 /* init interrupt nest, and context in thread sp */
95 rt_interrupt_nest = 0;
96 rt_interrupt_from_thread = 0;
97 rt_interrupt_to_thread = 0;
98 rt_thread_switch_interrupt_flag = 0;
99 }
100
101 /**
102 * This function will mask a interrupt.
103 * @param vector the interrupt number
104 */
rt_hw_interrupt_mask(int vector)105 void rt_hw_interrupt_mask(int vector)
106 {
107 INTC_MIR_SET(AINTC_BASE, vector >> 0x05) = 0x1 << (vector & 0x1f);
108 }
109
110 /**
111 * This function will un-mask a interrupt.
112 * @param vector the interrupt number
113 */
rt_hw_interrupt_umask(int vector)114 void rt_hw_interrupt_umask(int vector)
115 {
116 INTC_MIR_CLEAR(AINTC_BASE, vector >> 0x05) = 0x1 << (vector & 0x1f);
117 }
118
119 /**
120 * This function will control the interrupt attribute.
121 * @param vector the interrupt number
122 */
rt_hw_interrupt_control(int vector,int priority,int route)123 void rt_hw_interrupt_control(int vector, int priority, int route)
124 {
125 int fiq;
126
127 if (route == 0)
128 fiq = 0;
129 else
130 fiq = 1;
131
132 INTC_ILR(AINTC_BASE, vector) = ((priority << 0x02) & 0x1FC) | fiq ;
133 }
134
rt_hw_interrupt_get_active(int fiq_irq)135 int rt_hw_interrupt_get_active(int fiq_irq)
136 {
137 int ir;
138 if (fiq_irq == INT_FIQ)
139 {
140 ir = INTC_SIR_FIQ(AINTC_BASE) & 0x7f;
141 }
142 else
143 {
144 ir = INTC_SIR_IRQ(AINTC_BASE) & 0x7f;
145 }
146
147 return ir;
148 }
149
rt_hw_interrupt_ack(int fiq_irq)150 void rt_hw_interrupt_ack(int fiq_irq)
151 {
152 if (fiq_irq == INT_FIQ)
153 {
154 /* new FIQ generation */
155 INTC_CONTROL(AINTC_BASE) |= 0x02;
156 }
157 else
158 {
159 /* new IRQ generation */
160 INTC_CONTROL(AINTC_BASE) |= 0x01;
161 }
162 }
163
164 /**
165 * This function will install a interrupt service routine to a interrupt.
166 * @param vector the interrupt number
167 * @param new_handler the interrupt service routine to be installed
168 * @param old_handler the old interrupt service routine
169 */
rt_hw_interrupt_install(int vector,rt_isr_handler_t handler,void * param,const char * name)170 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
171 void *param, const char *name)
172 {
173 rt_isr_handler_t old_handler = RT_NULL;
174
175 if(vector < MAX_HANDLERS)
176 {
177 old_handler = isr_table[vector].handler;
178
179 if (handler != RT_NULL)
180 {
181 #ifdef RT_USING_INTERRUPT_INFO
182 rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
183 #endif /* RT_USING_INTERRUPT_INFO */
184 isr_table[vector].handler = handler;
185 isr_table[vector].param = param;
186 }
187 }
188
189 return old_handler;
190 }
191
192 /**
193 * This function will trigger an interrupt.
194 * @param vector the interrupt number
195 */
rt_hw_interrupt_trigger(int vector)196 void rt_hw_interrupt_trigger(int vector)
197 {
198 INTC_ISR_SET(AINTC_BASE, vector>>5) = 1 << (vector & 0x1f);
199 }
200
rt_hw_interrupt_clear(int vector)201 void rt_hw_interrupt_clear(int vector)
202 {
203 INTC_ISR_CLEAR(AINTC_BASE, vector>>5) = 1 << (vector & 0x1f);
204 }
205
rt_dump_isr_table(void)206 void rt_dump_isr_table(void)
207 {
208 int idx;
209 for(idx = 0; idx < MAX_HANDLERS; idx++)
210 {
211 #ifdef RT_USING_INTERRUPT_INFO
212 rt_kprintf("nr:%4d, name: %*.s, handler: 0x%p, param: 0x%08x\r\n",
213 idx, RT_NAME_MAX, isr_table[idx].name,
214 isr_table[idx].handler, isr_table[idx].param);
215 #else
216 rt_kprintf("nr:%4d, handler: 0x%p, param: 0x%08x\r\n",
217 idx, isr_table[idx].handler, isr_table[idx].param);
218 #endif
219 }
220 }
221 /*@}*/
222
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224