1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2013-07-06     Bernard      first version
9  */
10 
11 #ifndef __INTERRUPT_H__
12 #define __INTERRUPT_H__
13 
14 #define INT_IRQ     0x00
15 #define INT_FIQ     0x01
16 
17 /*************************************************************************\
18  * Registers Definition
19 \*************************************************************************/
20 #define INTC_REVISION(hw_base)          REG32((hw_base) + 0x0)
21 #define INTC_SYSCONFIG(hw_base)         REG32((hw_base) + 0x10)
22 #define INTC_SYSSTATUS(hw_base)         REG32((hw_base) + 0x14)
23 #define INTC_SIR_IRQ(hw_base)           REG32((hw_base) + 0x40)
24 #define INTC_SIR_FIQ(hw_base)           REG32((hw_base) + 0x44)
25 #define INTC_CONTROL(hw_base)           REG32((hw_base) + 0x48)
26 #define INTC_PROTECTION(hw_base)        REG32((hw_base) + 0x4c)
27 #define INTC_IDLE(hw_base)              REG32((hw_base) + 0x50)
28 #define INTC_IRQ_PRIORITY(hw_base)      REG32((hw_base) + 0x60)
29 #define INTC_FIQ_PRIORITY(hw_base)      REG32((hw_base) + 0x64)
30 #define INTC_THRESHOLD(hw_base)         REG32((hw_base) + 0x68)
31 #define INTC_SICR(hw_base)              REG32((hw_base) + 0x6c)
32 #define INTC_SCR(hw_base, n)            REG32((hw_base) + 0x70 + ((n) * 0x04))
33 #define INTC_ITR(hw_base, n)            REG32((hw_base) + 0x80 + ((n) * 0x20))
34 #define INTC_MIR(hw_base, n)            REG32((hw_base) + 0x84 + ((n) * 0x20))
35 #define INTC_MIR_CLEAR(hw_base, n)      REG32((hw_base) + 0x88 + ((n) * 0x20))
36 #define INTC_MIR_SET(hw_base, n)        REG32((hw_base) + 0x8c + ((n) * 0x20))
37 #define INTC_ISR_SET(hw_base, n)        REG32((hw_base) + 0x90 + ((n) * 0x20))
38 #define INTC_ISR_CLEAR(hw_base, n)      REG32((hw_base) + 0x94 + ((n) * 0x20))
39 #define INTC_PENDING_IRQ(hw_base, n)    REG32((hw_base) + 0x98 + ((n) * 0x20))
40 #define INTC_PENDING_FIQ(hw_base, n)    REG32((hw_base) + 0x9c + ((n) * 0x20))
41 #define INTC_ILR(hw_base, n)            REG32((hw_base) + 0x100 + ((n) * 0x04))
42 
43 /**************************************************************************\
44 * Field Definition Macros
45 \**************************************************************************/
46 
47 /* REVISION */
48 #define INTC_REVISION_REV    (0x000000FFu)
49 #define INTC_REVISION_REV_SHIFT  (0x00000000u)
50 
51 /* SYSCONFIG */
52 #define INTC_SYSCONFIG_SOFTRESET    (0x00000002u)
53 #define INTC_SYSCONFIG_SOFTRESET_SHIFT  (0x00000001u)
54 
55 #define INTC_SYSCONFIG_AUTOIDLE    (0x00000001u)
56 #define INTC_SYSCONFIG_AUTOIDLE_SHIFT  (0x00000000u)
57 
58 /* SYSSTATUS */
59 #define INTC_SYSSTATUS_RESETDONE    (0x00000001u)
60 #define INTC_SYSSTATUS_RESETDONE_SHIFT  (0x00000000u)
61 
62 /* SIR_IRQ */
63 #define INTC_SIR_IRQ_SPURIOUSIRQ    (0xFFFFFF80u)
64 #define INTC_SIR_IRQ_SPURIOUSIRQ_SHIFT  (0x00000007u)
65 
66 #define INTC_SIR_IRQ_ACTIVEIRQ    (0x0000007F)
67 #define INTC_SIR_IRQ_ACTIVEIRQ_SHIFT  (0x00000000)
68 
69 /* SIR_FIQ */
70 #define INTC_SIR_FIQ_SPURIOUSFIQ    (0xFFFFFF80)
71 #define INTC_SIR_FIQ_SPURIOUSFIQ_SHIFT  (0x00000007)
72 
73 #define INTC_SIR_FIQ_ACTIVEFIQ    (0x0000007F)
74 #define INTC_SIR_FIQ_ACTIVEFIQ_SHIFT  (0x00000000)
75 
76 /* CONTROL */
77 #define INTC_CONTROL_NEWFIQAGR    (0x00000002)
78 #define INTC_CONTROL_NEWFIQAGR_SHIFT  (0x00000001)
79 
80 #define INTC_CONTROL_NEWIRQAGR    (0x00000001)
81 #define INTC_CONTROL_NEWIRQAGR_SHIFT  (0x00000000)
82 
83 /* PROTECTION */
84 #define INTC_PROTECTION_PROTECTION    (0x00000001u)
85 #define INTC_PROTECTION_PROTECTION_SHIFT  (0x00000000u)
86 
87 /* IDLE */
88 #define INTC_IDLE_TURBO    (0x00000002u)
89 #define INTC_IDLE_TURBO_SHIFT  (0x00000001u)
90 
91 #define INTC_IDLE_FUNCIDLE    (0x00000001u)
92 #define INTC_IDLE_FUNCIDLE_SHIFT  (0x00000000u)
93 
94 /* IRQ_PRIORITY */
95 #define INTC_IRQ_PRIORITY_SPURIOUSIRQFLAG    (0xFFFFFFC0u)
96 #define INTC_IRQ_PRIORITY_SPURIOUSIRQFLAG_SHIFT  (0x00000006u)
97 
98 #define INTC_IRQ_PRIORITY_IRQPRIORITY    (0x0000003Fu)
99 #define INTC_IRQ_PRIORITY_IRQPRIORITY_SHIFT  (0x00000000u)
100 
101 /* FIQ_PRIORITY */
102 #define INTC_FIQ_PRIORITY_SPURIOUSFIQFLAG    (0xFFFFFFC0u)
103 #define INTC_FIQ_PRIORITY_SPURIOUSFIQFLAG_SHIFT  (0x00000006u)
104 
105 #define INTC_FIQ_PRIORITY_FIQPRIORITY    (0x0000003Fu)
106 #define INTC_FIQ_PRIORITY_FIQPRIORITY_SHIFT  (0x00000000u)
107 
108 /* THRESHOLD */
109 #define INTC_THRESHOLD_PRIORITYTHRESHOLD    (0x000000FFu)
110 #define INTC_THRESHOLD_PRIORITYTHRESHOLD_SHIFT  (0x00000000u)
111 
112 /* SICR */
113 #define INTC_SICR_GLOBALMASK    (0x00000040u)
114 #define INTC_SICR_GLOBALMASK_SHIFT  (0x00000006u)
115 
116 #define INTC_SICR_SOFTRESETINH    (0x00000020u)
117 #define INTC_SICR_SOFTRESETINH_SHIFT  (0x00000005u)
118 
119 #define INTC_SICR_PUBLICMASKFEEDBACK    (0x00000010u)
120 #define INTC_SICR_PUBLICMASKFEEDBACK_SHIFT  (0x00000004u)
121 
122 #define INTC_SICR_PUBLICINHIBIT    (0x00000008u)
123 #define INTC_SICR_PUBLICINHIBIT_SHIFT  (0x00000003u)
124 
125 #define INTC_SICR_AUTOINHIBIT    (0x00000004u)
126 #define INTC_SICR_AUTOINHIBIT_SHIFT  (0x00000002u)
127 
128 #define INTC_SICR_SSMFIQENABLE    (0x00000002u)
129 #define INTC_SICR_SSMFIQENABLE_SHIFT  (0x00000001u)
130 
131 #define INTC_SICR_SSMFIQSTATUS    (0x00000001u)
132 #define INTC_SICR_SSMFIQSTATUS_SHIFT  (0x00000000u)
133 
134 /* SCR0 */
135 #define INTC_SCR0_SECUREENABLE    (0xFFFFFFFFu)
136 #define INTC_SCR0_SECUREENABLE_SHIFT  (0x00000000u)
137 
138 /* SCR1 */
139 #define INTC_SCR1_SECUREENABLE    (0xFFFFFFFFu)
140 #define INTC_SCR1_SECUREENABLE_SHIFT  (0x00000000u)
141 
142 /* SCR2 */
143 #define INTC_SCR2_SECUREENABLE    (0xFFFFFFFFu)
144 #define INTC_SCR2_SECUREENABLE_SHIFT  (0x00000000u)
145 
146 /* ITR0 */
147 #define INTC_ITR0_ITR    (0xFFFFFFFFu)
148 #define INTC_ITR0_ITR_SHIFT  (0x00000000u)
149 
150 /* MIR0 */
151 #define INTC_MIR0_MIR    (0xFFFFFFFFu)
152 #define INTC_MIR0_MIR_SHIFT  (0x00000000u)
153 
154 /* MIR_CLEAR0 */
155 #define INTC_MIR_CLEAR0_MIRCLEAR    (0xFFFFFFFFu)
156 #define INTC_MIR_CLEAR0_MIRCLEAR_SHIFT  (0x00000000u)
157 
158 /* MIR_SET0 */
159 #define INTC_MIR_SET0_MIRSET    (0xFFFFFFFFu)
160 #define INTC_MIR_SET0_MIRSET_SHIFT  (0x00000000u)
161 
162 /* ISR_SET0 */
163 #define INTC_ISR_SET0_ISRSET    (0xFFFFFFFFu)
164 #define INTC_ISR_SET0_ISRSET_SHIFT  (0x00000000u)
165 
166 /* ISR_CLEAR0 */
167 #define INTC_ISR_CLEAR0_ISRCLEAR    (0xFFFFFFFFu)
168 #define INTC_ISR_CLEAR0_ISRCLEAR_SHIFT  (0x00000000u)
169 
170 /* PENDING_IRQ0 */
171 #define INTC_PENDING_IRQ0_PENDING_IRQ    (0xFFFFFFFFu)
172 #define INTC_PENDING_IRQ0_PENDING_IRQ_SHIFT  (0x00000000u)
173 
174 /* PENDING_FIQ0 */
175 #define INTC_PENDING_FIQ0_PENDING_FIQ    (0xFFFFFFFFu)
176 #define INTC_PENDING_FIQ0_PENDING_FIQ_SHIFT  (0x00000000u)
177 
178 /* ITR1 */
179 #define INTC_ITR1_ITR    (0xFFFFFFFFu)
180 #define INTC_ITR1_ITR_SHIFT  (0x00000000u)
181 
182 /* MIR1 */
183 #define INTC_MIR1_MIR    (0xFFFFFFFFu)
184 #define INTC_MIR1_MIR_SHIFT  (0x00000000u)
185 
186 /* MIR_CLEAR1 */
187 #define INTC_MIR_CLEAR1_MIRCLEAR    (0xFFFFFFFFu)
188 #define INTC_MIR_CLEAR1_MIRCLEAR_SHIFT  (0x00000000u)
189 
190 /* MIR_SET1 */
191 #define INTC_MIR_SET1_MIRSET    (0xFFFFFFFFu)
192 #define INTC_MIR_SET1_MIRSET_SHIFT  (0x00000000u)
193 
194 /* ISR_SET1 */
195 #define INTC_ISR_SET1_ISRSET    (0xFFFFFFFFu)
196 #define INTC_ISR_SET1_ISRSET_SHIFT  (0x00000000u)
197 
198 /* ISR_CLEAR1 */
199 #define INTC_ISR_CLEAR1_ISRCLEAR    (0xFFFFFFFFu)
200 #define INTC_ISR_CLEAR1_ISRCLEAR_SHIFT  (0x00000000u)
201 
202 /* PENDING_IRQ1 */
203 #define INTC_PENDING_IRQ1_PENDING_IRQ    (0xFFFFFFFFu)
204 #define INTC_PENDING_IRQ1_PENDING_IRQ_SHIFT  (0x00000000u)
205 
206 /* PENDING_FIQ1 */
207 #define INTC_PENDING_FIQ1_PENDING_FIQ    (0xFFFFFFFFu)
208 #define INTC_PENDING_FIQ1_PENDING_FIQ_SHIFT  (0x00000000u)
209 
210 /* ITR2 */
211 #define INTC_ITR2_ITR    (0xFFFFFFFFu)
212 #define INTC_ITR2_ITR_SHIFT  (0x00000000u)
213 
214 /* MIR2 */
215 #define INTC_MIR2_MIR    (0xFFFFFFFFu)
216 #define INTC_MIR2_MIR_SHIFT  (0x00000000u)
217 
218 /* MIR_CLEAR2 */
219 #define INTC_MIR_CLEAR2_MIRCLEAR    (0xFFFFFFFFu)
220 #define INTC_MIR_CLEAR2_MIRCLEAR_SHIFT  (0x00000000u)
221 
222 /* MIR_SET2 */
223 #define INTC_MIR_SET2_MIRSET    (0xFFFFFFFFu)
224 #define INTC_MIR_SET2_MIRSET_SHIFT  (0x00000000u)
225 
226 /* ISR_SET2 */
227 #define INTC_ISR_SET2_ISRSET    (0xFFFFFFFFu)
228 #define INTC_ISR_SET2_ISRSET_SHIFT  (0x00000000u)
229 
230 /* ISR_CLEAR2 */
231 #define INTC_ISR_CLEAR2_ISRCLEAR    (0xFFFFFFFFu)
232 #define INTC_ISR_CLEAR2_ISRCLEAR_SHIFT  (0x00000000u)
233 
234 /* PENDING_IRQ2 */
235 #define INTC_PENDING_IRQ2_PENDING_IRQ    (0xFFFFFFFFu)
236 #define INTC_PENDING_IRQ2_PENDING_IRQ_SHIFT  (0x00000000u)
237 
238 /* PENDING_FIQ2 */
239 #define INTC_PENDING_FIQ2_PENDING_FIQ    (0xFFFFFFFFu)
240 #define INTC_PENDING_FIQ2_PENDING_FIQ_SHIFT  (0x00000000u)
241 
242 /* ILR */
243 #define INTC_ILR_PRIORITY    (0x000001FCu)
244 #define INTC_ILR_PRIORITY_SHIFT  (0x00000002u)
245 
246 #define INTC_ILR_FIQNIRQ    (0x00000001u)
247 #define INTC_ILR_FIQNIRQ_SHIFT  (0x00000000u)
248 
249 void rt_hw_interrupt_control(int vector, int priority, int route);
250 int rt_hw_interrupt_get_active(int fiq_irq);
251 void rt_hw_interrupt_ack(int fiq_irq);
252 void rt_hw_interrupt_trigger(int vector);
253 void rt_hw_interrupt_clear(int vector);
254 
255 #endif
256