1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2018-03-25     quanzhao     the first version
9  */
10 #ifndef __CP15_H__
11 #define __CP15_H__
12 
13 #define __get_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MRC p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : "=r" (Rt) : : "memory" )
14 #define __set_cp(cp, op1, Rt, CRn, CRm, op2) __asm__ volatile("MCR p" # cp ", " # op1 ", %0, c" # CRn ", c" # CRm ", " # op2 : : "r" (Rt) : "memory" )
15 #define __get_cp64(cp, op1, Rt, CRm) __asm__ volatile("MRRC p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : "=r" (Rt) : : "memory" )
16 #define __set_cp64(cp, op1, Rt, CRm) __asm__ volatile("MCRR p" # cp ", " # op1 ", %Q0, %R0, c" # CRm  : : "r" (Rt) : "memory" )
17 
18 int rt_hw_cpu_id(void);
19 void rt_cpu_mmu_disable(void);
20 void rt_cpu_mmu_enable(void);
21 void rt_cpu_tlb_set(volatile unsigned long*);
22 
23 void rt_cpu_dcache_clean_flush(void);
24 void rt_cpu_icache_flush(void);
25 
26 void rt_cpu_vector_set_base(unsigned int addr);
27 
28 #endif
29