1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2013-07-20     Bernard      first version
9  */
10 
11 #ifndef __GIC_V3_H__
12 #define __GIC_V3_H__
13 
14 #include <rthw.h>
15 #include <board.h>
16 
17 #define __get_gicv3_reg(CR, Rt) __asm__ volatile("MRC " CR  \
18                                                  : "=r"(Rt) \
19                                                  :          \
20                                                  : "memory")
21 #define __set_gicv3_reg(CR, Rt) __asm__ volatile("MCR " CR \
22                                                  :         \
23                                                  : "r"(Rt) \
24                                                  : "memory")
25 
26 
27 /* AArch32 System register interface to GICv3 */
28 #define ICC_IAR0    "p15, 0, %0, c12, c8, 0"
29 #define ICC_IAR1    "p15, 0, %0, c12, c12, 0"
30 #define ICC_EOIR0   "p15, 0, %0, c12, c8, 1"
31 #define ICC_EOIR1   "p15, 0, %0, c12, c12, 1"
32 #define ICC_HPPIR0  "p15, 0, %0, c12, c8, 2"
33 #define ICC_HPPIR1  "p15, 0, %0, c12, c12, 2"
34 #define ICC_BPR0    "p15, 0, %0, c12, c8, 3"
35 #define ICC_BPR1    "p15, 0, %0, c12, c12, 3"
36 #define ICC_DIR     "p15, 0, %0, c12, c11, 1"
37 #define ICC_PMR     "p15, 0, %0, c4, c6, 0"
38 #define ICC_RPR     "p15, 0, %0, c12, c11, 3"
39 #define ICC_CTLR    "p15, 0, %0, c12, c12, 4"
40 #define ICC_MCTLR   "p15, 6, %0, c12, c12, 4"
41 #define ICC_SRE     "p15, 0, %0, c12, c12, 5"
42 #define ICC_HSRE    "p15, 4, %0, c12, c9, 5"
43 #define ICC_MSRE    "p15, 6, %0, c12, c12, 5"
44 #define ICC_IGRPEN0 "p15, 0, %0, c12, c12, 6"
45 #define ICC_IGRPEN1 "p15, 0, %0, c12, c12, 7"
46 #define ICC_MGRPEN1 "p15, 6, %0, c12, c12, 7"
47 
48 #define __REG32(x) (*((volatile unsigned int*)((rt_uint32_t)x)))
49 
50 #define ROUTED_TO_ALL (1)
51 #define ROUTED_TO_SPEC (0)
52 
53 /** Macro to access the Distributor Control Register (GICD_CTLR)
54 */
55 #define GICD_CTLR_RWP (1<<31)
56 #define GICD_CTLR_E1NWF (1<<7)
57 #define GICD_CTLR_DS (1<<6)
58 #define GICD_CTLR_ARE_NS (1<<5)
59 #define GICD_CTLR_ARE_S (1<<4)
60 #define GICD_CTLR_ENGRP1S (1<<2)
61 #define GICD_CTLR_ENGRP1NS (1<<1)
62 #define GICD_CTLR_ENGRP0 (1<<0)
63 
64 /** Macro to access the Redistributor Control Register (GICR_CTLR)
65 */
66 #define GICR_CTLR_UWP (1<<31)
67 #define GICR_CTLR_DPG1S (1<<26)
68 #define GICR_CTLR_DPG1NS (1<<25)
69 #define GICR_CTLR_DPG0 (1<<24)
70 #define GICR_CTLR_RWP (1<<3)
71 #define GICR_CTLR_IR (1<<2)
72 #define GICR_CTLR_CES (1<<1)
73 #define GICR_CTLR_EnableLPI (1<<0)
74 
75 /** Macro to access the Generic Interrupt Controller Interface (GICC)
76 */
77 #define GIC_CPU_CTRL(hw_base)               __REG32((hw_base) + 0x00U)
78 #define GIC_CPU_PRIMASK(hw_base)            __REG32((hw_base) + 0x04U)
79 #define GIC_CPU_BINPOINT(hw_base)           __REG32((hw_base) + 0x08U)
80 #define GIC_CPU_INTACK(hw_base)             __REG32((hw_base) + 0x0cU)
81 #define GIC_CPU_EOI(hw_base)                __REG32((hw_base) + 0x10U)
82 #define GIC_CPU_RUNNINGPRI(hw_base)         __REG32((hw_base) + 0x14U)
83 #define GIC_CPU_HIGHPRI(hw_base)            __REG32((hw_base) + 0x18U)
84 #define GIC_CPU_IIDR(hw_base)               __REG32((hw_base) + 0xFCU)
85 
86 /** Macro to access the Generic Interrupt Controller Distributor (GICD)
87 */
88 #define GIC_DIST_CTRL(hw_base)              __REG32((hw_base) + 0x000U)
89 #define GIC_DIST_TYPE(hw_base)              __REG32((hw_base) + 0x004U)
90 #define GIC_DIST_IGROUP(hw_base, n)         __REG32((hw_base) + 0x080U + ((n)/32U) * 4U)
91 #define GIC_DIST_ENABLE_SET(hw_base, n)     __REG32((hw_base) + 0x100U + ((n)/32U) * 4U)
92 #define GIC_DIST_ENABLE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x180U + ((n)/32U) * 4U)
93 #define GIC_DIST_PENDING_SET(hw_base, n)    __REG32((hw_base) + 0x200U + ((n)/32U) * 4U)
94 #define GIC_DIST_PENDING_CLEAR(hw_base, n)  __REG32((hw_base) + 0x280U + ((n)/32U) * 4U)
95 #define GIC_DIST_ACTIVE_SET(hw_base, n)     __REG32((hw_base) + 0x300U + ((n)/32U) * 4U)
96 #define GIC_DIST_ACTIVE_CLEAR(hw_base, n)   __REG32((hw_base) + 0x380U + ((n)/32U) * 4U)
97 #define GIC_DIST_PRI(hw_base, n)            __REG32((hw_base) + 0x400U + ((n)/4U) * 4U)
98 #define GIC_DIST_TARGET(hw_base, n)         __REG32((hw_base) + 0x800U + ((n)/4U) * 4U)
99 #define GIC_DIST_CONFIG(hw_base, n)         __REG32((hw_base) + 0xc00U + ((n)/16U) * 4U)
100 #define GIC_DIST_SOFTINT(hw_base)           __REG32((hw_base) + 0xf00U)
101 #define GIC_DIST_CPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf10U + ((n)/4U) * 4U)
102 #define GIC_DIST_SPENDSGI(hw_base, n)       __REG32((hw_base) + 0xf20U + ((n)/4U) * 4U)
103 #define GIC_DIST_ICPIDR2(hw_base)           __REG32((hw_base) + 0xfe8U)
104 #define GIC_DIST_IROUTER_LOW(hw_base, n)    __REG32((hw_base) + 0x6000U + (n)*8U)
105 #define GIC_DIST_IROUTER_HIGH(hw_base, n)   __REG32((hw_base) + 0x6000U + (n)*8U + 4)
106 
107 /* SGI base address  is at 64K offset from Redistributor base address */
108 #define GIC_RSGI_OFFSET 0x10000
109 
110 /** Macro to access the Generic Interrupt Controller Redistributor (GICD)
111 */
112 #define GIC_RDIST_CTRL(hw_base)              __REG32((hw_base) + 0x000U)
113 #define GIC_RDIST_IIDR(hw_base)              __REG32((hw_base) + 0x004U)
114 #define GIC_RDIST_TYPER(hw_base)             __REG32((hw_base) + 0x008U)
115 #define GIC_RDIST_TSTATUSR(hw_base)          __REG32((hw_base) + 0x010U)
116 #define GIC_RDIST_WAKER(hw_base)             __REG32((hw_base) + 0x014U)
117 #define GIC_RDIST_SETLPIR(hw_base)           __REG32((hw_base) + 0x040U)
118 #define GIC_RDIST_CLRLPIR(hw_base)           __REG32((hw_base) + 0x048U)
119 #define GIC_RDIST_PROPBASER(hw_base)         __REG32((hw_base) + 0x070U)
120 #define GIC_RDIST_PENDBASER(hw_base)         __REG32((hw_base) + 0x078U)
121 #define GIC_RDIST_INVLPIR(hw_base)           __REG32((hw_base) + 0x0A0U)
122 #define GIC_RDIST_INVALLR(hw_base)           __REG32((hw_base) + 0x0B0U)
123 #define GIC_RDIST_SYNCR(hw_base)             __REG32((hw_base) + 0x0C0U)
124 
125 #define GIC_RDISTSGI_IGROUPR0(hw_base, n)    __REG32((hw_base) + GIC_RSGI_OFFSET + 0x080U + (n)*4U)
126 #define GIC_RDISTSGI_ISENABLER0(hw_base)     __REG32((hw_base) + GIC_RSGI_OFFSET + 0x100U)
127 #define GIC_RDISTSGI_ICENABLER0(hw_base)     __REG32((hw_base) + GIC_RSGI_OFFSET + 0x180U)
128 #define GIC_RDISTSGI_ISPENDR0(hw_base)       __REG32((hw_base) + GIC_RSGI_OFFSET + 0x200U)
129 #define GIC_RDISTSGI_ICPENDR0(hw_base)       __REG32((hw_base) + GIC_RSGI_OFFSET + 0x280U)
130 #define GIC_RDISTSGI_ISACTIVER0(hw_base)     __REG32((hw_base) + GIC_RSGI_OFFSET + 0x300U)
131 #define GIC_RDISTSGI_ICACTIVER0(hw_base)     __REG32((hw_base) + GIC_RSGI_OFFSET + 0x380U)
132 #define GIC_RDISTSGI_IPRIORITYR(hw_base, n)  __REG32((hw_base) + GIC_RSGI_OFFSET + 0x400U + ((n) / 4U) * 4U)
133 #define GIC_RDISTSGI_ICFGR0(hw_base)         __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC00U)
134 #define GIC_RDISTSGI_ICFGR1(hw_base)         __REG32((hw_base) + GIC_RSGI_OFFSET + 0xC04U)
135 #define GIC_RDISTSGI_IGRPMODR0(hw_base, n)   __REG32((hw_base) + GIC_RSGI_OFFSET + 0xD00U + (n)*4)
136 #define GIC_RDISTSGI_NSACR(hw_base)          __REG32((hw_base) + GIC_RSGI_OFFSET + 0xE00U)
137 
138 #define GIC_RSGI_AFF1_OFFSET    16
139 #define GIC_RSGI_AFF2_OFFSET    32
140 #define GIC_RSGI_AFF3_OFFSET    48
141 
142 rt_uint32_t arm_gic_cpumask_to_affval(rt_uint32_t *cpu_mask, rt_uint32_t *cluster_id, rt_uint32_t *target_list);
143 rt_uint64_t get_main_cpu_affval(void);
144 int arm_gic_get_active_irq(rt_uint32_t index);
145 void arm_gic_ack(rt_uint32_t index, int irq);
146 
147 void arm_gic_mask(rt_uint32_t index, int irq);
148 void arm_gic_umask(rt_uint32_t index, int irq);
149 
150 rt_uint32_t arm_gic_get_pending_irq(rt_uint32_t index, int irq);
151 void arm_gic_set_pending_irq(rt_uint32_t index, int irq);
152 void arm_gic_clear_pending_irq(rt_uint32_t index, int irq);
153 
154 void arm_gic_set_configuration(rt_uint32_t index, int irq, rt_uint32_t config);
155 rt_uint32_t arm_gic_get_configuration(rt_uint32_t index, int irq);
156 
157 void arm_gic_clear_active(rt_uint32_t index, int irq);
158 
159 void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask);
160 rt_uint32_t arm_gic_get_target_cpu(rt_uint32_t index, int irq);
161 
162 void arm_gic_set_priority(rt_uint32_t index, int irq, rt_uint32_t priority);
163 rt_uint32_t arm_gic_get_priority(rt_uint32_t index, int irq);
164 
165 void arm_gic_set_interface_prior_mask(rt_uint32_t index, rt_uint32_t priority);
166 rt_uint32_t arm_gic_get_interface_prior_mask(rt_uint32_t index);
167 
168 void arm_gic_set_binary_point(rt_uint32_t index, rt_uint32_t binary_point);
169 rt_uint32_t arm_gic_get_binary_point(rt_uint32_t index);
170 
171 rt_uint32_t arm_gic_get_irq_status(rt_uint32_t index, int irq);
172 
173 void arm_gic_send_affinity_sgi(rt_uint32_t index, int irq, rt_uint32_t cpu_mask, rt_uint32_t routing_mode);
174 rt_uint32_t arm_gic_get_high_pending_irq(rt_uint32_t index);
175 
176 rt_uint32_t arm_gic_get_interface_id(rt_uint32_t index);
177 
178 void arm_gic_set_group(rt_uint32_t index, int irq, rt_uint32_t group);
179 rt_uint32_t arm_gic_get_group(rt_uint32_t index, int irq);
180 
181 int arm_gic_redist_address_set(rt_uint32_t index, rt_uint32_t redist_addr, rt_uint32_t cpu_id);
182 int arm_gic_cpu_interface_address_set(rt_uint32_t index, rt_uint32_t interface_addr, rt_uint32_t cpu_id);
183 int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start);
184 int arm_gic_cpu_init(rt_uint32_t index);
185 int arm_gic_redist_init(rt_uint32_t index);
186 
187 void arm_gic_dump_type(rt_uint32_t index);
188 void arm_gic_dump(rt_uint32_t index);
189 
190 void arm_gic_set_system_register_enable_mask(rt_uint32_t index, rt_uint32_t value);
191 rt_uint32_t arm_gic_get_system_register_enable_mask(rt_uint32_t index);
192 void arm_gic_secondary_cpu_init(void);
193 #endif
194 
195