1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2009-01-05 Bernard first version
9 * 2011-02-14 onelife Modify for EFM32
10 * 2011-06-17 onelife Merge all of the C source code into cpuport.c
11 * 2012-12-23 aozima stack addr align to 8byte.
12 * 2012-12-29 Bernard Add exception hook.
13 * 2013-07-09 aozima enhancement hard fault exception handler.
14 * 2019-07-03 yangjie add __rt_ffs() for armclang.
15 */
16
17 #include <rtthread.h>
18
19 struct exception_stack_frame
20 {
21 rt_uint32_t r0;
22 rt_uint32_t r1;
23 rt_uint32_t r2;
24 rt_uint32_t r3;
25 rt_uint32_t r12;
26 rt_uint32_t lr;
27 rt_uint32_t pc;
28 rt_uint32_t psr;
29 };
30
31 struct stack_frame
32 {
33 /* r4 ~ r11 register */
34 rt_uint32_t r4;
35 rt_uint32_t r5;
36 rt_uint32_t r6;
37 rt_uint32_t r7;
38 rt_uint32_t r8;
39 rt_uint32_t r9;
40 rt_uint32_t r10;
41 rt_uint32_t r11;
42
43 struct exception_stack_frame exception_stack_frame;
44 };
45
46 /* flag in interrupt handling */
47 rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
48 rt_uint32_t rt_thread_switch_interrupt_flag;
49 /* exception hook */
50 static rt_err_t (*rt_exception_hook)(void *context) = RT_NULL;
51
52 /**
53 * This function will initialize thread stack
54 *
55 * @param tentry the entry of thread
56 * @param parameter the parameter of entry
57 * @param stack_addr the beginning stack address
58 * @param texit the function will be called when thread exit
59 *
60 * @return stack address
61 */
rt_hw_stack_init(void * tentry,void * parameter,rt_uint8_t * stack_addr,void * texit)62 rt_uint8_t *rt_hw_stack_init(void *tentry,
63 void *parameter,
64 rt_uint8_t *stack_addr,
65 void *texit)
66 {
67 struct stack_frame *stack_frame;
68 rt_uint8_t *stk;
69 unsigned long i;
70
71 stk = stack_addr + sizeof(rt_uint32_t);
72 stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_uint32_t)stk, 8);
73 stk -= sizeof(struct stack_frame);
74
75 stack_frame = (struct stack_frame *)stk;
76
77 /* init all register */
78 for (i = 0; i < sizeof(struct stack_frame) / sizeof(rt_uint32_t); i ++)
79 {
80 ((rt_uint32_t *)stack_frame)[i] = 0xdeadbeef;
81 }
82
83 stack_frame->exception_stack_frame.r0 = (unsigned long)parameter; /* r0 : argument */
84 stack_frame->exception_stack_frame.r1 = 0; /* r1 */
85 stack_frame->exception_stack_frame.r2 = 0; /* r2 */
86 stack_frame->exception_stack_frame.r3 = 0; /* r3 */
87 stack_frame->exception_stack_frame.r12 = 0; /* r12 */
88 stack_frame->exception_stack_frame.lr = (unsigned long)texit; /* lr */
89 stack_frame->exception_stack_frame.pc = (unsigned long)tentry; /* entry point, pc */
90 stack_frame->exception_stack_frame.psr = 0x01000000L; /* PSR */
91
92 /* return task's current stack address */
93 return stk;
94 }
95
96 /**
97 * This function set the hook, which is invoked on fault exception handling.
98 *
99 * @param exception_handle the exception handling hook function.
100 */
rt_hw_exception_install(rt_err_t (* exception_handle)(void * context))101 void rt_hw_exception_install(rt_err_t (*exception_handle)(void* context))
102 {
103 rt_exception_hook = exception_handle;
104 }
105
106 #define SCB_CFSR (*(volatile const unsigned *)0xE000ED28) /* Configurable Fault Status Register */
107 #define SCB_HFSR (*(volatile const unsigned *)0xE000ED2C) /* HardFault Status Register */
108 #define SCB_MMAR (*(volatile const unsigned *)0xE000ED34) /* MemManage Fault Address register */
109 #define SCB_BFAR (*(volatile const unsigned *)0xE000ED38) /* Bus Fault Address Register */
110 #define SCB_AIRCR (*(volatile unsigned long *)0xE000ED0C) /* Reset control Address Register */
111 #define SCB_RESET_VALUE 0x05FA0004 /* Reset value, write to SCB_AIRCR can reset cpu */
112
113 #define SCB_CFSR_MFSR (*(volatile const unsigned char*)0xE000ED28) /* Memory-management Fault Status Register */
114 #define SCB_CFSR_BFSR (*(volatile const unsigned char*)0xE000ED29) /* Bus Fault Status Register */
115 #define SCB_CFSR_UFSR (*(volatile const unsigned short*)0xE000ED2A) /* Usage Fault Status Register */
116
117 #ifdef RT_USING_FINSH
usage_fault_track(void)118 static void usage_fault_track(void)
119 {
120 rt_kprintf("usage fault:\n");
121 rt_kprintf("SCB_CFSR_UFSR:0x%02X ", SCB_CFSR_UFSR);
122
123 if(SCB_CFSR_UFSR & (1<<0))
124 {
125 /* [0]:UNDEFINSTR */
126 rt_kprintf("UNDEFINSTR ");
127 }
128
129 if(SCB_CFSR_UFSR & (1<<1))
130 {
131 /* [1]:INVSTATE */
132 rt_kprintf("INVSTATE ");
133 }
134
135 if(SCB_CFSR_UFSR & (1<<2))
136 {
137 /* [2]:INVPC */
138 rt_kprintf("INVPC ");
139 }
140
141 if(SCB_CFSR_UFSR & (1<<3))
142 {
143 /* [3]:NOCP */
144 rt_kprintf("NOCP ");
145 }
146
147 if(SCB_CFSR_UFSR & (1<<8))
148 {
149 /* [8]:UNALIGNED */
150 rt_kprintf("UNALIGNED ");
151 }
152
153 if(SCB_CFSR_UFSR & (1<<9))
154 {
155 /* [9]:DIVBYZERO */
156 rt_kprintf("DIVBYZERO ");
157 }
158
159 rt_kprintf("\n");
160 }
161
bus_fault_track(void)162 static void bus_fault_track(void)
163 {
164 rt_kprintf("bus fault:\n");
165 rt_kprintf("SCB_CFSR_BFSR:0x%02X ", SCB_CFSR_BFSR);
166
167 if(SCB_CFSR_BFSR & (1<<0))
168 {
169 /* [0]:IBUSERR */
170 rt_kprintf("IBUSERR ");
171 }
172
173 if(SCB_CFSR_BFSR & (1<<1))
174 {
175 /* [1]:PRECISERR */
176 rt_kprintf("PRECISERR ");
177 }
178
179 if(SCB_CFSR_BFSR & (1<<2))
180 {
181 /* [2]:IMPRECISERR */
182 rt_kprintf("IMPRECISERR ");
183 }
184
185 if(SCB_CFSR_BFSR & (1<<3))
186 {
187 /* [3]:UNSTKERR */
188 rt_kprintf("UNSTKERR ");
189 }
190
191 if(SCB_CFSR_BFSR & (1<<4))
192 {
193 /* [4]:STKERR */
194 rt_kprintf("STKERR ");
195 }
196
197 if(SCB_CFSR_BFSR & (1<<7))
198 {
199 rt_kprintf("SCB->BFAR:%08X\n", SCB_BFAR);
200 }
201 else
202 {
203 rt_kprintf("\n");
204 }
205 }
206
mem_manage_fault_track(void)207 static void mem_manage_fault_track(void)
208 {
209 rt_kprintf("mem manage fault:\n");
210 rt_kprintf("SCB_CFSR_MFSR:0x%02X ", SCB_CFSR_MFSR);
211
212 if(SCB_CFSR_MFSR & (1<<0))
213 {
214 /* [0]:IACCVIOL */
215 rt_kprintf("IACCVIOL ");
216 }
217
218 if(SCB_CFSR_MFSR & (1<<1))
219 {
220 /* [1]:DACCVIOL */
221 rt_kprintf("DACCVIOL ");
222 }
223
224 if(SCB_CFSR_MFSR & (1<<3))
225 {
226 /* [3]:MUNSTKERR */
227 rt_kprintf("MUNSTKERR ");
228 }
229
230 if(SCB_CFSR_MFSR & (1<<4))
231 {
232 /* [4]:MSTKERR */
233 rt_kprintf("MSTKERR ");
234 }
235
236 if(SCB_CFSR_MFSR & (1<<7))
237 {
238 /* [7]:MMARVALID */
239 rt_kprintf("SCB->MMAR:%08X\n", SCB_MMAR);
240 }
241 else
242 {
243 rt_kprintf("\n");
244 }
245 }
246
hard_fault_track(void)247 static void hard_fault_track(void)
248 {
249 if(SCB_HFSR & (1UL<<1))
250 {
251 /* [1]:VECTBL, Indicates hard fault is caused by failed vector fetch. */
252 rt_kprintf("failed vector fetch\n");
253 }
254
255 if(SCB_HFSR & (1UL<<30))
256 {
257 /* [30]:FORCED, Indicates hard fault is taken because of bus fault,
258 memory management fault, or usage fault. */
259 if(SCB_CFSR_BFSR)
260 {
261 bus_fault_track();
262 }
263
264 if(SCB_CFSR_MFSR)
265 {
266 mem_manage_fault_track();
267 }
268
269 if(SCB_CFSR_UFSR)
270 {
271 usage_fault_track();
272 }
273 }
274
275 if(SCB_HFSR & (1UL<<31))
276 {
277 /* [31]:DEBUGEVT, Indicates hard fault is triggered by debug event. */
278 rt_kprintf("debug event\n");
279 }
280 }
281 #endif /* RT_USING_FINSH */
282
283 struct exception_info
284 {
285 rt_uint32_t exc_return;
286 struct stack_frame stack_frame;
287 };
288
289 /*
290 * fault exception handler
291 */
rt_hw_hard_fault_exception(struct exception_info * exception_info)292 void rt_hw_hard_fault_exception(struct exception_info * exception_info)
293 {
294 #if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
295 extern long list_thread(void);
296 #endif
297 struct exception_stack_frame *exception_stack = &exception_info->stack_frame.exception_stack_frame;
298 struct stack_frame *context = &exception_info->stack_frame;
299
300 if (rt_exception_hook != RT_NULL)
301 {
302 rt_err_t result;
303
304 result = rt_exception_hook(exception_stack);
305 if (result == RT_EOK)
306 return;
307 }
308
309 rt_kprintf("psr: 0x%08x\n", context->exception_stack_frame.psr);
310
311 rt_kprintf("r00: 0x%08x\n", context->exception_stack_frame.r0);
312 rt_kprintf("r01: 0x%08x\n", context->exception_stack_frame.r1);
313 rt_kprintf("r02: 0x%08x\n", context->exception_stack_frame.r2);
314 rt_kprintf("r03: 0x%08x\n", context->exception_stack_frame.r3);
315 rt_kprintf("r04: 0x%08x\n", context->r4);
316 rt_kprintf("r05: 0x%08x\n", context->r5);
317 rt_kprintf("r06: 0x%08x\n", context->r6);
318 rt_kprintf("r07: 0x%08x\n", context->r7);
319 rt_kprintf("r08: 0x%08x\n", context->r8);
320 rt_kprintf("r09: 0x%08x\n", context->r9);
321 rt_kprintf("r10: 0x%08x\n", context->r10);
322 rt_kprintf("r11: 0x%08x\n", context->r11);
323 rt_kprintf("r12: 0x%08x\n", context->exception_stack_frame.r12);
324 rt_kprintf(" lr: 0x%08x\n", context->exception_stack_frame.lr);
325 rt_kprintf(" pc: 0x%08x\n", context->exception_stack_frame.pc);
326
327 if(exception_info->exc_return & (1 << 2) )
328 {
329 rt_kprintf("hard fault on thread: %s\r\n\r\n", rt_thread_self()->parent.name);
330
331 #if defined(RT_USING_FINSH) && defined(MSH_USING_BUILT_IN_COMMANDS)
332 list_thread();
333 #endif
334 }
335 else
336 {
337 rt_kprintf("hard fault on handler\r\n\r\n");
338 }
339
340 #ifdef RT_USING_FINSH
341 hard_fault_track();
342 #endif /* RT_USING_FINSH */
343
344 while (1);
345 }
346
347 /**
348 * reset CPU
349 */
rt_hw_cpu_reset(void)350 void rt_hw_cpu_reset(void)
351 {
352 SCB_AIRCR = SCB_RESET_VALUE;
353 }
354
355 #ifdef RT_USING_CPU_FFS
356 /**
357 * This function finds the first bit set (beginning with the least significant bit)
358 * in value and return the index of that bit.
359 *
360 * Bits are numbered starting at 1 (the least significant bit). A return value of
361 * zero from any of these functions means that the argument was zero.
362 *
363 * @return return the index of the first bit set. If value is 0, then this function
364 * shall return 0.
365 */
366 #if defined(__CC_ARM)
__rt_ffs(int value)367 __asm int __rt_ffs(int value)
368 {
369 CMP r0, #0x00
370 BEQ exit
371
372 RBIT r0, r0
373 CLZ r0, r0
374 ADDS r0, r0, #0x01
375
376 exit
377 BX lr
378 }
379 #elif defined(__clang__)
__rt_ffs(int value)380 int __rt_ffs(int value)
381 {
382 __asm volatile(
383 "CMP %1, #0x00 \n"
384 "BEQ 1f \n"
385
386 "RBIT %1, %1 \n"
387 "CLZ %0, %1 \n"
388 "ADDS %0, %0, #0x01 \n"
389
390 "1: \n"
391
392 : "=r"(value)
393 : "r"(value)
394 );
395 return value;
396 }
397 #elif defined(__IAR_SYSTEMS_ICC__)
__rt_ffs(int value)398 int __rt_ffs(int value)
399 {
400 if (value == 0) return value;
401
402 asm("RBIT %0, %1" : "=r"(value) : "r"(value));
403 asm("CLZ %0, %1" : "=r"(value) : "r"(value));
404 asm("ADDS %0, %1, #0x01" : "=r"(value) : "r"(value));
405
406 return value;
407 }
408 #elif defined(__GNUC__)
__rt_ffs(int value)409 int __rt_ffs(int value)
410 {
411 return __builtin_ffs(value);
412 }
413 #endif
414
415 #endif
416