1;/*
2; * Copyright (c) 2006-2018, RT-Thread Development Team
3; *
4; * SPDX-License-Identifier: Apache-2.0
5; *
6; * Change Logs:
7; * Date           Author       Notes
8; * 2009-01-17     Bernard      first version
9; * 2009-09-27     Bernard      add protect when contex switch occurs
10; * 2012-01-01     aozima       support context switch load/store FPU register.
11; * 2013-06-18     aozima       add restore MSP feature.
12; * 2013-06-23     aozima       support lazy stack optimized.
13; * 2018-07-24     aozima       enhancement hard fault exception handler.
14; * 2024-08-13     Evlers       allows rewrite to interrupt enable/disable api to support independent interrupts management
15; */
16
17;/**
18; * @addtogroup cortex-m4
19; */
20;/*@{*/
21
22SCB_VTOR        EQU     0xE000ED08               ; Vector Table Offset Register
23NVIC_INT_CTRL   EQU     0xE000ED04               ; interrupt control state register
24NVIC_SYSPRI2    EQU     0xE000ED20               ; system priority register (2)
25NVIC_PENDSV_PRI EQU     0xFFFF0000               ; PendSV and SysTick priority value (lowest)
26NVIC_PENDSVSET  EQU     0x10000000               ; value to trigger PendSV exception
27
28    SECTION    .text:CODE(2)
29    THUMB
30    REQUIRE8
31    PRESERVE8
32
33    IMPORT rt_thread_switch_interrupt_flag
34    IMPORT rt_interrupt_from_thread
35    IMPORT rt_interrupt_to_thread
36
37;/*
38; * rt_base_t rt_hw_interrupt_disable();
39; */
40    PUBWEAK rt_hw_interrupt_disable
41    SECTION .text:CODE:REORDER:NOROOT(2)
42rt_hw_interrupt_disable:
43    MRS     r0, PRIMASK
44    CPSID   I
45    BX      LR
46
47;/*
48; * void rt_hw_interrupt_enable(rt_base_t level);
49; */
50    PUBWEAK  rt_hw_interrupt_enable
51    SECTION .text:CODE:REORDER:NOROOT(2)
52rt_hw_interrupt_enable:
53    MSR     PRIMASK, r0
54    BX      LR
55
56;/*
57; * void rt_hw_context_switch(rt_uint32 from, rt_uint32 to);
58; * r0 --> from
59; * r1 --> to
60; */
61    EXPORT rt_hw_context_switch_interrupt
62    EXPORT rt_hw_context_switch
63rt_hw_context_switch_interrupt:
64rt_hw_context_switch:
65    ; set rt_thread_switch_interrupt_flag to 1
66    LDR     r2, =rt_thread_switch_interrupt_flag
67    LDR     r3, [r2]
68    CMP     r3, #1
69    BEQ     _reswitch
70    MOV     r3, #1
71    STR     r3, [r2]
72
73    LDR     r2, =rt_interrupt_from_thread   ; set rt_interrupt_from_thread
74    STR     r0, [r2]
75
76_reswitch
77    LDR     r2, =rt_interrupt_to_thread     ; set rt_interrupt_to_thread
78    STR     r1, [r2]
79
80    LDR     r0, =NVIC_INT_CTRL              ; trigger the PendSV exception (causes context switch)
81    LDR     r1, =NVIC_PENDSVSET
82    STR     r1, [r0]
83    BX      LR
84
85; r0 --> switch from thread stack
86; r1 --> switch to thread stack
87; psr, pc, lr, r12, r3, r2, r1, r0 are pushed into [from] stack
88    EXPORT PendSV_Handler
89PendSV_Handler:
90
91    ; disable interrupt to protect context switch
92    MRS     r2, PRIMASK
93    CPSID   I
94
95    ; get rt_thread_switch_interrupt_flag
96    LDR     r0, =rt_thread_switch_interrupt_flag
97    LDR     r1, [r0]
98    CBZ     r1, pendsv_exit         ; pendsv already handled
99
100    ; clear rt_thread_switch_interrupt_flag to 0
101    MOV     r1, #0x00
102    STR     r1, [r0]
103
104    LDR     r0, =rt_interrupt_from_thread
105    LDR     r1, [r0]
106    CBZ     r1, switch_to_thread    ; skip register save at the first time
107
108    MRS     r1, psp                 ; get from thread stack pointer
109
110#if defined ( __ARMVFP__ )
111    TST     lr, #0x10               ; if(!EXC_RETURN[4])
112    BNE     skip_push_fpu
113    VSTMDB  r1!, {d8 - d15}         ; push FPU register s16~s31
114skip_push_fpu
115#endif
116
117    STMFD   r1!, {r4 - r11}         ; push r4 - r11 register
118
119#if defined ( __ARMVFP__ )
120    MOV     r4, #0x00               ; flag = 0
121    TST     lr, #0x10               ; if(!EXC_RETURN[4])
122    BNE     push_flag
123    MOV     r4, #0x01               ; flag = 1
124push_flag
125    ;STMFD   r1!, {r4}              ; push flag
126    SUB     r1, r1, #0x04
127    STR     r4, [r1]
128#endif
129
130    LDR     r0, [r0]
131    STR     r1, [r0]                ; update from thread stack pointer
132
133switch_to_thread
134    LDR     r1, =rt_interrupt_to_thread
135    LDR     r1, [r1]
136    LDR     r1, [r1]                ; load thread stack pointer
137
138#if defined ( __ARMVFP__ )
139    LDMFD   r1!, {r3}               ; pop flag
140#endif
141
142    LDMFD   r1!, {r4 - r11}         ; pop r4 - r11 register
143
144#if defined ( __ARMVFP__ )
145    CBZ     r3, skip_pop_fpu
146    VLDMIA  r1!, {d8 - d15}         ; pop FPU register s16~s31
147skip_pop_fpu
148#endif
149
150    MSR     psp, r1                 ; update stack pointer
151
152#if defined ( __ARMVFP__ )
153    ORR     lr, lr, #0x10           ; lr |=  (1 << 4), clean FPCA.
154    CBZ     r3, return_without_fpu  ; if(flag_r3 != 0)
155    BIC     lr, lr, #0x10           ; lr &= ~(1 << 4), set FPCA.
156return_without_fpu
157#endif
158
159pendsv_exit
160    ; restore interrupt
161    MSR     PRIMASK, r2
162
163    ORR     lr, lr, #0x04
164    BX      lr
165
166;/*
167; * void rt_hw_context_switch_to(rt_uint32 to);
168; * r0 --> to
169; */
170    EXPORT rt_hw_context_switch_to
171rt_hw_context_switch_to:
172    LDR     r1, =rt_interrupt_to_thread
173    STR     r0, [r1]
174
175#if defined ( __ARMVFP__ )
176    ; CLEAR CONTROL.FPCA
177    MRS     r2, CONTROL             ; read
178    BIC     r2, r2, #0x04           ; modify
179    MSR     CONTROL, r2             ; write-back
180#endif
181
182    ; set from thread to 0
183    LDR     r1, =rt_interrupt_from_thread
184    MOV     r0, #0x0
185    STR     r0, [r1]
186
187    ; set interrupt flag to 1
188    LDR     r1, =rt_thread_switch_interrupt_flag
189    MOV     r0, #1
190    STR     r0, [r1]
191
192    ; set the PendSV and SysTick exception priority
193    LDR     r0, =NVIC_SYSPRI2
194    LDR     r1, =NVIC_PENDSV_PRI
195    LDR.W   r2, [r0,#0x00]       ; read
196    ORR     r1,r1,r2             ; modify
197    STR     r1, [r0]             ; write-back
198
199    LDR     r0, =NVIC_INT_CTRL      ; trigger the PendSV exception (causes context switch)
200    LDR     r1, =NVIC_PENDSVSET
201    STR     r1, [r0]
202
203    ; restore MSP
204    LDR     r0, =SCB_VTOR
205    LDR     r0, [r0]
206    LDR     r0, [r0]
207    NOP
208    MSR     msp, r0
209
210    ; enable interrupts at processor level
211    CPSIE   F
212    CPSIE   I
213
214    ; clear the BASEPRI register to disable masking priority
215    MOV     r0, #0x00
216    MSR     BASEPRI, r0
217
218    ; ensure PendSV exception taken place before subsequent operation
219    DSB
220    ISB
221
222    ; never reach here!
223
224; compatible with old version
225    EXPORT rt_hw_interrupt_thread_switch
226rt_hw_interrupt_thread_switch:
227    BX      lr
228
229    IMPORT rt_hw_hard_fault_exception
230    EXPORT HardFault_Handler
231HardFault_Handler:
232
233    ; get current context
234    MRS     r0, msp                 ; get fault context from handler.
235    TST     lr, #0x04               ; if(!EXC_RETURN[2])
236    BEQ     _get_sp_done
237    MRS     r0, psp                 ; get fault context from thread.
238_get_sp_done
239
240#if defined ( __ARMVFP__ )
241    TST     lr, #0x10               ; if(!EXC_RETURN[4])
242    BNE     skip_push_fpu
243    VSTMDB  r0!, {d8 - d15}         ; push FPU register s16~s31
244skip_push_fpu
245#endif
246
247    STMFD   r0!, {r4 - r11}         ; push r4 - r11 register
248
249#if defined ( __ARMVFP__ )
250    MOV     r4, #0x00               ; flag = 0
251
252    TST     lr, #0x10               ; if(!EXC_RETURN[4])
253    BNE     push_flag
254    MOV     r4, #0x01               ; flag = 1
255push_flag
256    SUB     r0, r0, #0x04
257    STR     r4, [r0]                ; push flag
258#endif
259
260    SUB     r0, r0, #0x04
261    STR     lr, [r0]                ; push exec_return register
262
263    TST     lr, #0x04               ; if(!EXC_RETURN[2])
264    BEQ     _update_msp
265    MSR     psp, r0                 ; update stack pointer to PSP.
266    B       _update_done
267_update_msp
268    MSR     msp, r0                 ; update stack pointer to MSP.
269_update_done
270
271    PUSH    {lr}
272    BL      rt_hw_hard_fault_exception
273    POP     {lr}
274
275    ORR     lr, lr, #0x04
276    BX      lr
277
278    END
279