1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2008-12-11 XuXinming first version
9 * 2013-05-24 Grissiom port to RM48x50
10 */
11
12 #include <rtthread.h>
13
14 /**
15 * @addtogroup RM48x50
16 */
17 /*@{*/
18
19 #ifdef __TI_COMPILER_VERSION__
20 #ifdef RT_USING_CPU_FFS
__rt_ffs(int value)21 int __rt_ffs(int value)
22 {
23 if (value == 0)
24 return value;
25
26 __asm(" rsb r1, r0, #0");
27 __asm(" and r1, r1, r0");
28 __asm(" clz r1, r1");
29 __asm(" rsb r0, r1, #32");
30 }
31 #endif
32
rt_hw_cpu_icache_enable()33 void rt_hw_cpu_icache_enable()
34 {
35 __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
36 __asm(" ORR r1, r1, #0x1 <<12 ; instruction cache enable");
37 __asm(" MCR p15, #0, r0, c7, c5, #0 ; Invalidate entire instruction cache, r0 is ignored");
38 __asm(" MCR p15, #0, r1, c1, c0, #0 ; enabled instruction cache");
39 __asm(" ISB");
40 }
41
rt_hw_cpu_icache_disable()42 void rt_hw_cpu_icache_disable()
43 {
44 __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
45 __asm(" BIC r1, r1, #0x1 <<12 ; instruction cache enable");
46 __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled instruction cache");
47 __asm(" ISB");
48 }
49
rt_hw_cpu_dcache_enable()50 void rt_hw_cpu_dcache_enable()
51 {
52 __asm(" MRC p15, #0, R1, c1, c0, #0 ; Read SCTLR configuration data");
53 __asm(" ORR R1, R1, #0x1 <<2");
54 __asm(" DSB");
55 __asm(" MCR p15, #0, r0, c15, c5, #0 ; Invalidate entire data cache");
56 __asm(" MCR p15, #0, R1, c1, c0, #0 ; enabled data cache");
57 }
58
rt_hw_cpu_dcache_disable()59 void rt_hw_cpu_dcache_disable()
60 {
61 /* FIXME: Clean entire data cache. This routine depends on the data cache
62 * size. It can be omitted if it is known that the data cache has no dirty
63 * data. */
64 __asm(" MRC p15, #0, r1, c1, c0, #0 ; Read SCTLR configuration data");
65 __asm(" BIC r1, r1, #0x1 <<2");
66 __asm(" DSB");
67 __asm(" MCR p15, #0, r1, c1, c0, #0 ; disabled data cache");
68 }
69
70 #elif __GNUC__
71 #ifdef RT_USING_CPU_FFS
__rt_ffs(int value)72 int __rt_ffs(int value)
73 {
74 return __builtin_ffs(value);
75 }
76 #endif
77 #endif
78 /*@}*/
79