1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2013-07-06 Bernard first version
9 * 2014-04-03 Grissiom port to VMM
10 */
11
12 #include <rthw.h>
13 #include <rtthread.h>
14 #include "realview.h"
15 #include "gic.h"
16
17 #define MAX_HANDLERS NR_IRQS_PBA8
18
19 extern volatile rt_atomic_t rt_interrupt_nest;
20
21 /* exception and interrupt handler table */
22 struct rt_irq_desc isr_table[MAX_HANDLERS];
23
24 /* Those varibles will be accessed in ISR, so we need to share them. */
25 rt_uint32_t rt_interrupt_from_thread rt_section(".bss.share.int");
26 rt_uint32_t rt_interrupt_to_thread rt_section(".bss.share.int");
27 rt_uint32_t rt_thread_switch_interrupt_flag rt_section(".bss.share.int");
28
29 const unsigned int VECTOR_BASE = 0x00;
30 extern void rt_cpu_vector_set_base(unsigned int addr);
31 extern int system_vectors;
32
rt_hw_vector_init(void)33 static void rt_hw_vector_init(void)
34 {
35
36 }
37
38 /**
39 * This function will initialize hardware interrupt
40 */
rt_hw_interrupt_init(void)41 void rt_hw_interrupt_init(void)
42 {
43 rt_uint32_t gic_cpu_base;
44 rt_uint32_t gic_dist_base;
45
46 /* initialize vector table */
47 rt_hw_vector_init();
48
49 /* initialize exceptions table */
50 rt_memset(isr_table, 0x00, sizeof(isr_table));
51
52 /* initialize ARM GIC */
53 gic_dist_base = REALVIEW_GIC_DIST_BASE;
54 gic_cpu_base = REALVIEW_GIC_CPU_BASE;
55
56 arm_gic_dist_init(0, gic_dist_base, 0);
57 arm_gic_cpu_init(0, gic_cpu_base);
58 /*arm_gic_dump_type(0);*/
59
60 /* init interrupt nest, and context in thread sp */
61 rt_interrupt_nest = 0;
62 rt_interrupt_from_thread = 0;
63 rt_interrupt_to_thread = 0;
64 rt_thread_switch_interrupt_flag = 0;
65 }
66
67 /**
68 * This function will mask a interrupt.
69 * @param vector the interrupt number
70 */
rt_hw_interrupt_mask(int vector)71 void rt_hw_interrupt_mask(int vector)
72 {
73 arm_gic_mask(0, vector);
74 }
75
76 /**
77 * This function will un-mask a interrupt.
78 * @param vector the interrupt number
79 */
rt_hw_interrupt_umask(int vector)80 void rt_hw_interrupt_umask(int vector)
81 {
82 arm_gic_umask(0, vector);
83 }
84
85 /**
86 * This function will install a interrupt service routine to a interrupt.
87 * @param vector the interrupt number
88 * @param new_handler the interrupt service routine to be installed
89 * @param old_handler the old interrupt service routine
90 */
rt_hw_interrupt_install(int vector,rt_isr_handler_t handler,void * param,const char * name)91 rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler,
92 void *param, const char *name)
93 {
94 rt_isr_handler_t old_handler = RT_NULL;
95
96 if (vector < MAX_HANDLERS)
97 {
98 old_handler = isr_table[vector].handler;
99
100 if (handler != RT_NULL)
101 {
102 #ifdef RT_USING_INTERRUPT_INFO
103 rt_strncpy(isr_table[vector].name, name, RT_NAME_MAX);
104 #endif /* RT_USING_INTERRUPT_INFO */
105 isr_table[vector].handler = handler;
106 isr_table[vector].param = param;
107 }
108 }
109
110 return old_handler;
111 }
112
113 /**
114 * Trigger a software IRQ
115 *
116 * Since we are running in single core, the target CPU are always CPU0.
117 */
rt_hw_interrupt_trigger(int vector)118 void rt_hw_interrupt_trigger(int vector)
119 {
120 arm_gic_trigger(0, 1, vector);
121 }
122
rt_hw_interrupt_clear(int vector)123 void rt_hw_interrupt_clear(int vector)
124 {
125 arm_gic_clear_sgi(0, 1, vector);
126 }
127