1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2006-03-13 Bernard first version
9 */
10
11 #include <rtthread.h>
12 #include <sep4020.h>
13
14 extern rt_base_t rt_hw_interrupt_disable(void);
15
16 //TODO
17 #warning I DON'T KNOW IF THE MMU OPERATION WORKS ON SEP4020
18
19 /**
20 * @addtogroup S3C24X0
21 */
22 /*@{*/
23
24 #define ICACHE_MASK (rt_uint32_t)(1 << 12)
25 #define DCACHE_MASK (rt_uint32_t)(1 << 2)
26
27 #ifdef __GNUC__
cp15_rd(void)28 rt_inline rt_uint32_t cp15_rd(void)
29 {
30 rt_uint32_t i;
31
32 asm ("mrc p15, 0, %0, c1, c0, 0":"=r" (i));
33 return i;
34 }
35
36 rt_inline void cache_enable(rt_uint32_t bit)
37 {
38 __asm__ __volatile__( \
39 "mrc p15,0,r0,c1,c0,0\n\t" \
40 "orr r0,r0,%0\n\t" \
41 "mcr p15,0,r0,c1,c0,0" \
42 : \
43 :"r" (bit) \
44 :"memory");
45 }
46
47 rt_inline void cache_disable(rt_uint32_t bit)
48 {
49 __asm__ __volatile__( \
50 "mrc p15,0,r0,c1,c0,0\n\t" \
51 "bic r0,r0,%0\n\t" \
52 "mcr p15,0,r0,c1,c0,0" \
53 : \
54 :"r" (bit) \
55 :"memory");
56 }
57 #endif
58
59 #ifdef __CC_ARM
60 rt_inline rt_uint32_t cp15_rd(void)
61 {
62 rt_uint32_t i;
63
64 __asm
65 {
66 mrc p15, 0, i, c1, c0, 0
67 }
68
69 return i;
70 }
71
72 rt_inline void cache_enable(rt_uint32_t bit)
73 {
74 rt_uint32_t value;
75
76 __asm
77 {
78 mrc p15, 0, value, c1, c0, 0
79 orr value, value, bit
80 mcr p15, 0, value, c1, c0, 0
81 }
82 }
83
84 rt_inline void cache_disable(rt_uint32_t bit)
85 {
86 rt_uint32_t value;
87
88 __asm
89 {
90 mrc p15, 0, value, c1, c0, 0
91 bic value, value, bit
92 mcr p15, 0, value, c1, c0, 0
93 }
94 }
95 #endif
96
97 /**
98 * enable I-Cache
99 *
100 */
101 void rt_hw_cpu_icache_enable()
102 {
103 cache_enable(ICACHE_MASK);
104 }
105
106 /**
107 * disable I-Cache
108 *
109 */
110 void rt_hw_cpu_icache_disable()
111 {
112 cache_disable(ICACHE_MASK);
113 }
114
115 /**
116 * return the status of I-Cache
117 *
118 */
119 rt_base_t rt_hw_cpu_icache_status()
120 {
121 return (cp15_rd() & ICACHE_MASK);
122 }
123
124 /**
125 * enable D-Cache
126 *
127 */
128 void rt_hw_cpu_dcache_enable()
129 {
130 cache_enable(DCACHE_MASK);
131 }
132
133 /**
134 * disable D-Cache
135 *
136 */
137 void rt_hw_cpu_dcache_disable()
138 {
139 cache_disable(DCACHE_MASK);
140 }
141
142 /**
143 * return the status of D-Cache
144 *
145 */
146 rt_base_t rt_hw_cpu_dcache_status()
147 {
148 return (cp15_rd() & DCACHE_MASK);
149 }
150
151 /**
152 * reset cpu by dog's time-out
153 *
154 */
155 void rt_hw_cpu_reset()
156 {
157
158 /* enable watchdog */
159 *(RP)(RTC_CTR) = 0x02;
160
161 /*Enable watchdog reset*/
162 *(RP)(RTC_INT_EN) = 0x20;
163
164 /* Initialize watchdog timer count register */
165 *(RP)(RTC_WD_CNT) = 0x0001;
166
167 while(1); /* loop forever and wait for reset to happen */
168
169 /* NEVER REACHED */
170 }
171
172 /*@}*/
173