1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2020-03-19 WangHuachen first version
9 */
10
11 #include <rtthread.h>
12 #include "board.h"
13 #include "gic.h"
14
15 /* ZynqMP-RPU uses the Arm PL-390 generic interrupt controller that is
16 * compliant to the GICv1 architecture specification. */
17
18 struct arm_gic
19 {
20 rt_uint32_t offset;
21
22 rt_uint32_t dist_hw_base;
23 rt_uint32_t cpu_hw_base;
24 };
25
26 static struct arm_gic _gic_table[ARM_GIC_MAX_NR];
27
28 #define GIC_CPU_CTRL(hw_base) __REG32((hw_base) + 0x00)
29 #define GIC_CPU_PRIMASK(hw_base) __REG32((hw_base) + 0x04)
30 #define GIC_CPU_BINPOINT(hw_base) __REG32((hw_base) + 0x08)
31 #define GIC_CPU_INTACK(hw_base) __REG32((hw_base) + 0x0c)
32 #define GIC_CPU_EOI(hw_base) __REG32((hw_base) + 0x10)
33 #define GIC_CPU_RUNNINGPRI(hw_base) __REG32((hw_base) + 0x14)
34 #define GIC_CPU_HIGHPRI(hw_base) __REG32((hw_base) + 0x18)
35
36 #define GIC_DIST_CTRL(hw_base) __REG32((hw_base) + 0x000)
37 #define GIC_DIST_TYPE(hw_base) __REG32((hw_base) + 0x004)
38 #define GIC_DIST_IGROUP(hw_base, n) __REG32((hw_base) + 0x080 + ((n)/32) * 4)
39 #define GIC_DIST_ENABLE_SET(hw_base, n) __REG32((hw_base) + 0x100 + ((n)/32) * 4)
40 #define GIC_DIST_ENABLE_CLEAR(hw_base, n) __REG32((hw_base) + 0x180 + ((n)/32) * 4)
41 #define GIC_DIST_PENDING_SET(hw_base, n) __REG32((hw_base) + 0x200 + ((n)/32) * 4)
42 #define GIC_DIST_PENDING_CLEAR(hw_base, n) __REG32((hw_base) + 0x280 + ((n)/32) * 4)
43 #define GIC_DIST_ACTIVE_SET(hw_base, n) __REG32((hw_base) + 0x300 + ((n)/32) * 4)
44 #define GIC_DIST_PRI(hw_base, n) __REG32((hw_base) + 0x400 + ((n)/4) * 4)
45 #define GIC_DIST_TARGET(hw_base, n) __REG32((hw_base) + 0x800 + ((n)/4) * 4)
46 #define GIC_DIST_CONFIG(hw_base, n) __REG32((hw_base) + 0xc00 + ((n)/16) * 4)
47 #define GIC_DIST_SOFTINT(hw_base) __REG32((hw_base) + 0xf00)
48 #define GIC_DIST_ICPIDR2(hw_base) __REG32((hw_base) + 0xfe8)
49
50 static unsigned int _gic_max_irq;
51
arm_gic_get_active_irq(rt_uint32_t index)52 int arm_gic_get_active_irq(rt_uint32_t index)
53 {
54 int irq;
55
56 RT_ASSERT(index < ARM_GIC_MAX_NR);
57
58 irq = GIC_CPU_INTACK(_gic_table[index].cpu_hw_base);
59 irq += _gic_table[index].offset;
60 return irq;
61 }
62
arm_gic_ack(rt_uint32_t index,int irq)63 void arm_gic_ack(rt_uint32_t index, int irq)
64 {
65 rt_uint32_t mask = 1 << (irq % 32);
66
67 RT_ASSERT(index < ARM_GIC_MAX_NR);
68
69 irq = irq - _gic_table[index].offset;
70 RT_ASSERT(irq >= 0);
71
72 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
73 GIC_CPU_EOI(_gic_table[index].cpu_hw_base) = irq;
74 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
75 }
76
arm_gic_mask(rt_uint32_t index,int irq)77 void arm_gic_mask(rt_uint32_t index, int irq)
78 {
79 rt_uint32_t mask = 1 << (irq % 32);
80
81 RT_ASSERT(index < ARM_GIC_MAX_NR);
82
83 irq = irq - _gic_table[index].offset;
84 RT_ASSERT(irq >= 0);
85
86 GIC_DIST_ENABLE_CLEAR(_gic_table[index].dist_hw_base, irq) = mask;
87 }
88
arm_gic_set_cpu(rt_uint32_t index,int irq,unsigned int cpumask)89 void arm_gic_set_cpu(rt_uint32_t index, int irq, unsigned int cpumask)
90 {
91 rt_uint32_t old_tgt;
92
93 RT_ASSERT(index < ARM_GIC_MAX_NR);
94
95 irq = irq - _gic_table[index].offset;
96 RT_ASSERT(irq >= 0);
97
98 old_tgt = GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq);
99
100 old_tgt &= ~(0x0FFUL << ((irq % 4)*8));
101 old_tgt |= cpumask << ((irq % 4)*8);
102
103 GIC_DIST_TARGET(_gic_table[index].dist_hw_base, irq) = old_tgt;
104 }
105
arm_gic_umask(rt_uint32_t index,int irq)106 void arm_gic_umask(rt_uint32_t index, int irq)
107 {
108 rt_uint32_t mask = 1 << (irq % 32);
109
110 RT_ASSERT(index < ARM_GIC_MAX_NR);
111
112 irq = irq - _gic_table[index].offset;
113 RT_ASSERT(irq >= 0);
114
115 GIC_DIST_ENABLE_SET(_gic_table[index].dist_hw_base, irq) = mask;
116 }
117
arm_gic_dump_type(rt_uint32_t index)118 void arm_gic_dump_type(rt_uint32_t index)
119 {
120 unsigned int gic_type;
121
122 gic_type = GIC_DIST_TYPE(_gic_table[index].dist_hw_base);
123 rt_kprintf("GICv%d on %p, max IRQs: %d, %s security extension(%08x)\n",
124 (GIC_DIST_ICPIDR2(_gic_table[index].dist_hw_base) >> 4) & 0xf,
125 _gic_table[index].dist_hw_base,
126 _gic_max_irq,
127 gic_type & (1 << 10) ? "has" : "no",
128 gic_type);
129 }
130
arm_gic_dist_init(rt_uint32_t index,rt_uint32_t dist_base,int irq_start)131 int arm_gic_dist_init(rt_uint32_t index, rt_uint32_t dist_base, int irq_start)
132 {
133 unsigned int gic_type, i;
134 rt_uint32_t cpumask = 1 << 0;
135
136 RT_ASSERT(index < ARM_GIC_MAX_NR);
137
138 _gic_table[index].dist_hw_base = dist_base;
139 _gic_table[index].offset = irq_start;
140
141 /* Find out how many interrupts are supported. */
142 gic_type = GIC_DIST_TYPE(dist_base);
143 _gic_max_irq = ((gic_type & 0x1f) + 1) * 32;
144
145 /*
146 * The GIC only supports up to 1020 interrupt sources.
147 * Limit this to either the architected maximum, or the
148 * platform maximum.
149 */
150 if (_gic_max_irq > 1020)
151 _gic_max_irq = 1020;
152 if (_gic_max_irq > ARM_GIC_NR_IRQS)
153 _gic_max_irq = ARM_GIC_NR_IRQS;
154
155 cpumask |= cpumask << 8;
156 cpumask |= cpumask << 16;
157
158 GIC_DIST_CTRL(dist_base) = 0x0;
159
160 /* Set all global interrupts to be level triggered, active low. */
161 for (i = 32; i < _gic_max_irq; i += 16)
162 GIC_DIST_CONFIG(dist_base, i) = 0x0;
163
164 /* Set all global interrupts to this CPU only. */
165 for (i = 32; i < _gic_max_irq; i += 4)
166 GIC_DIST_TARGET(dist_base, i) = cpumask;
167
168 /* Set priority on all interrupts. */
169 for (i = 0; i < _gic_max_irq; i += 4)
170 GIC_DIST_PRI(dist_base, i) = 0xa0a0a0a0;
171
172 /* Disable all interrupts. */
173 for (i = 0; i < _gic_max_irq; i += 32)
174 GIC_DIST_ENABLE_CLEAR(dist_base, i) = 0xffffffff;
175
176 /* Enable interrupt. */
177 GIC_DIST_CTRL(dist_base) = 0x01;
178
179 return 0;
180 }
181
arm_gic_cpu_init(rt_uint32_t index,rt_uint32_t cpu_base)182 int arm_gic_cpu_init(rt_uint32_t index, rt_uint32_t cpu_base)
183 {
184 RT_ASSERT(index < ARM_GIC_MAX_NR);
185
186 _gic_table[index].cpu_hw_base = cpu_base;
187
188 GIC_CPU_PRIMASK(cpu_base) = 0xf0;
189 /* Enable CPU interrupt */
190 GIC_CPU_CTRL(cpu_base) = 0x01;
191
192 return 0;
193 }
194
arm_gic_trigger(rt_uint32_t index,int target_cpu,int irq)195 void arm_gic_trigger(rt_uint32_t index, int target_cpu, int irq)
196 {
197 unsigned int reg;
198
199 RT_ASSERT(irq <= 15);
200 RT_ASSERT(target_cpu <= 255);
201
202 reg = (target_cpu << 16) | irq;
203 GIC_DIST_SOFTINT(_gic_table[index].dist_hw_base) = reg;
204 }
205
arm_gic_clear_sgi(rt_uint32_t index,int target_cpu,int irq)206 void arm_gic_clear_sgi(rt_uint32_t index, int target_cpu, int irq)
207 {
208 /* SGI will be cleared automatically. */
209 }
210