1 /******************************************************************************
2 * Copyright (c) 2014 - 2020 Xilinx, Inc. All rights reserved.
3 * SPDX-License-Identifier: MIT
4 ******************************************************************************/
5
6 /*****************************************************************************/
7 /**
8 * @file mpu.c
9 *
10 * This file contains initial configuration of the MPU.
11 *
12 * <pre>
13 * MODIFICATION HISTORY:
14 *
15 * Ver Who Date Changes
16 * ----- ---- -------- ---------------------------------------------------
17 * 5.00 pkp 02/20/14 First release
18 * 5.04 pkp 12/18/15 Updated MPU initialization as per the proper address map
19 * 6.00 pkp 06/27/16 moving the Init_MPU code to .boot section since it is a
20 * part of processor boot process
21 * 6.2 mus 01/27/17 Updated to support IAR compiler
22 * 7.1 mus 09/11/19 Added warning message if DDR size is not in power of 2.
23 * Fix for CR#1038577.
24 * 7.2 asa 04/08/20 Fix warning in the function Init_MPU.
25 * </pre>
26 *
27 * @note
28 *
29 * None.
30 *
31 ******************************************************************************/
32 /***************************** Include Files *********************************/
33 #include <rtthread.h>
34 #include "zynqmp-r5.h"
35 #include "xreg_cortexr5.h"
36 #include "xpseudo_asm_gcc.h"
37
38 /***************** Macros (Inline Functions) Definitions *********************/
39
40 /**************************** Type Definitions *******************************/
41 typedef rt_int32_t s32;
42 typedef rt_uint64_t u64;
43 typedef rt_uint32_t u32;
44 /************************** Constant Definitions *****************************/
45
46 /************************** Variable Definitions *****************************/
47
48 static const struct {
49 u64 size;
50 unsigned int encoding;
51 }region_size[] = {
52 { 0x20, REGION_32B },
53 { 0x40, REGION_64B },
54 { 0x80, REGION_128B },
55 { 0x100, REGION_256B },
56 { 0x200, REGION_512B },
57 { 0x400, REGION_1K },
58 { 0x800, REGION_2K },
59 { 0x1000, REGION_4K },
60 { 0x2000, REGION_8K },
61 { 0x4000, REGION_16K },
62 { 0x8000, REGION_32K },
63 { 0x10000, REGION_64K },
64 { 0x20000, REGION_128K },
65 { 0x40000, REGION_256K },
66 { 0x80000, REGION_512K },
67 { 0x100000, REGION_1M },
68 { 0x200000, REGION_2M },
69 { 0x400000, REGION_4M },
70 { 0x800000, REGION_8M },
71 { 0x1000000, REGION_16M },
72 { 0x2000000, REGION_32M },
73 { 0x4000000, REGION_64M },
74 { 0x8000000, REGION_128M },
75 { 0x10000000, REGION_256M },
76 { 0x20000000, REGION_512M },
77 { 0x40000000, REGION_1G },
78 { 0x80000000, REGION_2G },
79 { 0x100000000, REGION_4G },
80 };
81
82 /************************** Function Prototypes ******************************/
83 #if defined (__GNUC__)
84 void Init_MPU(void) __attribute__((__section__(".boot")));
85 static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib) __attribute__((__section__(".boot")));
86 static void Xil_DisableMPURegions(void) __attribute__((__section__(".boot")));
87 #elif defined (__ICCARM__)
88 #pragma default_function_attributes = @ ".boot"
89 void Init_MPU(void);
90 static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib);
91 static void Xil_DisableMPURegions(void);
92 #endif
93 /*****************************************************************************
94 *
95 * Initialize MPU for a given address map and Enabled the background Region in
96 * MPU with default memory attributes for rest of address range for Cortex R5
97 * processor.
98 *
99 * @param None.
100 *
101 * @return None.
102 *
103 *
104 ******************************************************************************/
105
Init_MPU(void)106 void Init_MPU(void)
107 {
108 u32 Addr;
109 u32 RegSize = 0U;
110 u32 Attrib;
111 u32 RegNum = 0, i, Offset = 0;
112 u64 size;
113
114 Xil_DisableMPURegions();
115
116 Addr = 0x00000000U;
117 #ifdef XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR
118 /* If the DDR is present, configure region as per DDR size */
119 size = (XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR - XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR) + 1;
120 if (size < 0x80000000) {
121 /* Lookup the size. */
122 for (i = 0; i < sizeof region_size / sizeof region_size[0]; i++) {
123 if (size <= region_size[i].size) {
124 RegSize = region_size[i].encoding;
125
126 /* Check if DDR size is in power of 2*/
127 if ( XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR == 0x100000)
128 Offset = XPAR_PSU_R5_DDR_0_S_AXI_BASEADDR;
129 if (region_size[i].size > (size + Offset + 1)) {
130 rt_kprintf ("WARNING: DDR size mapped to Cortexr5 processor is not \
131 in power of 2. As processor allocates MPU regions size \
132 in power of 2, address range %llx to %x has been \
133 incorrectly mapped as normal memory \n", \
134 region_size[i].size - 1, ((u32)XPAR_PSU_R5_DDR_0_S_AXI_HIGHADDR + 1));
135 }
136 break;
137 }
138 }
139 } else {
140 /* if the DDR size is > 2GB, truncate it to 2GB */
141 RegSize = REGION_2G;
142 }
143 #else
144 /* For DDRless system, configure region for TCM */
145 RegSize = REGION_256K;
146 #endif
147 Attrib = NORM_NSHARED_WB_WA | PRIV_RW_USER_RW;
148 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
149 RegNum++;
150
151 /*
152 * 1G of strongly ordered memory from 0x80000000 to 0xBFFFFFFF for PL.
153 * 512 MB - LPD-PL interface
154 * 256 MB - FPD-PL (HPM0) interface
155 * 256 MB - FPD-PL (HPM1) interface
156 */
157 Addr = 0x80000000;
158 RegSize = REGION_1G;
159 Attrib = STRONG_ORDERD_SHARED | PRIV_RW_USER_RW ;
160 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
161 RegNum++;
162
163 /* 512M of device memory from 0xC0000000 to 0xDFFFFFFF for QSPI */
164 Addr = 0xC0000000U;
165 RegSize = REGION_512M;
166 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
167 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
168 RegNum++;
169
170 /* 256M of device memory from 0xE0000000 to 0xEFFFFFFF for PCIe Low */
171 Addr = 0xE0000000U;
172 RegSize = REGION_256M;
173 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
174 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
175 RegNum++;
176
177 /* 16M of device memory from 0xF8000000 to 0xF8FFFFFF for STM_CORESIGHT */
178 Addr = 0xF8000000U;
179 RegSize = REGION_16M;
180 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
181 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
182 RegNum++;
183
184 /* 1M of device memory from 0xF9000000 to 0xF90FFFFF for RPU_A53_GIC */
185 Addr = 0xF9000000U;
186 RegSize = REGION_1M;
187 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
188 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
189 RegNum++;
190
191 /* 16M of device memory from 0xFD000000 to 0xFDFFFFFF for FPS slaves */
192 Addr = 0xFD000000U;
193 RegSize = REGION_16M;
194 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
195 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
196 RegNum++;
197
198 /* 16M of device memory from 0xFE000000 to 0xFEFFFFFF for Upper LPS slaves */
199 Addr = 0xFE000000U;
200 RegSize = REGION_16M;
201 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
202 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
203 RegNum++;
204
205 /*
206 * 16M of device memory from 0xFF000000 to 0xFFFFFFFF for Lower LPS slaves,
207 * CSU, PMU, TCM, OCM
208 */
209 Addr = 0xFF000000U;
210 RegSize = REGION_16M;
211 Attrib = DEVICE_NONSHARED | PRIV_RW_USER_RW ;
212 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
213 RegNum++;
214
215 /* 256K of OCM RAM from 0xFFFC0000 to 0xFFFFFFFF marked as normal memory */
216 Addr = 0xFFFC0000U;
217 RegSize = REGION_256K;
218 Attrib = NORM_NSHARED_WB_WA| PRIV_RW_USER_RW ;
219 Xil_SetAttribute(Addr,RegSize,RegNum, Attrib);
220
221 /* A total of 10 MPU regions are allocated with another 6 being free for users */
222
223 }
224
225 /*****************************************************************************
226 *
227 * Set the memory attributes for a section of memory with starting address addr
228 * of the region size defined by reg_size having attributes attrib of region number
229 * reg_num
230 *
231 * @param addr is the address for which attributes are to be set.
232 * @param attrib specifies the attributes for that memory region.
233 * @param reg_size specifies the size for that memory region.
234 * @param reg_num specifies the number for that memory region.
235 * @return None.
236 *
237 *
238 ******************************************************************************/
Xil_SetAttribute(u32 addr,u32 reg_size,s32 reg_num,u32 attrib)239 static void Xil_SetAttribute(u32 addr, u32 reg_size,s32 reg_num, u32 attrib)
240 {
241 u32 Local_reg_size = reg_size;
242
243 Local_reg_size = Local_reg_size<<1U;
244 Local_reg_size |= REGION_EN;
245 dsb();
246 mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,reg_num);
247 isb();
248 mtcp(XREG_CP15_MPU_REG_BASEADDR,addr); /* Set base address of a region */
249 mtcp(XREG_CP15_MPU_REG_ACCESS_CTRL,attrib); /* Set the control attribute */
250 mtcp(XREG_CP15_MPU_REG_SIZE_EN,Local_reg_size); /* set the region size and enable it*/
251 dsb();
252 isb(); /* synchronize context on this processor */
253 }
254
255
256 /*****************************************************************************
257 *
258 * Disable all the MPU regions if any of them is enabled
259 *
260 * @param None.
261 *
262 * @return None.
263 *
264 *
265 ******************************************************************************/
Xil_DisableMPURegions(void)266 static void Xil_DisableMPURegions(void)
267 {
268 u32 Temp = 0U;
269 u32 Index = 0U;
270 for (Index = 0; Index <= 15; Index++) {
271 mtcp(XREG_CP15_MPU_MEMORY_REG_NUMBER,Index);
272 #if defined (__GNUC__)
273 Temp = mfcp(XREG_CP15_MPU_REG_SIZE_EN);
274 #elif defined (__ICCARM__)
275 mfcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
276 #endif
277 Temp &= (~REGION_EN);
278 dsb();
279 mtcp(XREG_CP15_MPU_REG_SIZE_EN,Temp);
280 dsb();
281 isb();
282 }
283
284 }
285
286 #if defined (__ICCARM__)
287 #pragma default_function_attributes =
288 #endif
289