1/*
2 * Copyright (c) 2006-2022, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date           Author       Notes
8 * 2010-04-09     fify         the first version
9 * 2010-04-19     fify         rewrite rt_hw_interrupt_disable/enable fuction
10 * 2010-04-20     fify         move peripheral ISR to bsp/interrupts.s34
11 */
12
13    RSEG    CSTACK
14
15    RSEG    ISTACK
16
17    RSEG    CODE(1)
18
19    EXTERN  rt_interrupt_from_thread
20    EXTERN  rt_interrupt_to_thread
21
22    PUBLIC  rt_hw_interrupt_disable
23    PUBLIC  rt_hw_interrupt_enable
24    PUBLIC  rt_hw_context_switch_to
25    PUBLIC  os_context_switch
26
27rt_hw_interrupt_disable:
28    STC     FLG, R0    ;fify 20100419
29    FCLR    I
30    RTS
31
32rt_hw_interrupt_enable:
33    LDC     R0, FLG    ;fify 20100419
34    RTS
35
36    .EVEN
37os_context_switch:
38    PUSHM   R0,R1,R2,R3,A0,A1,SB,FB
39
40    MOV.W   rt_interrupt_from_thread, A0
41    STC     ISP, [A0]
42    MOV.W   rt_interrupt_to_thread, A0
43    LDC     [A0], ISP
44
45    POPM    R0,R1,R2,R3,A0,A1,SB,FB             ; Restore registers from the new task's stack
46    REIT                                        ; Return from interrup
47
48/*
49 * void rt_hw_context_switch_to(rt_uint32 to);
50 * r0 --> to
51 * this fucntion is used to perform the first thread switch
52 */
53rt_hw_context_switch_to:
54    MOV.W   R0, A0
55    LDC     [A0], ISP
56    POPM    R0,R1,R2,R3,A0,A1,SB,FB
57    REIT
58
59    END
60