1/*
2 * Copyright (c) 2006-2022, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date           Author       Notes
8 * 2019-12-04     Jiaxun Yang  Initial version
9 * 2020-07-26     lizhirui     Add xtlb exception entry
10 */
11#ifndef __ASSEMBLY__
12#define __ASSEMBLY__
13#endif
14
15#include <mips.h>
16
17    .section ".exc_vectors", "ax"
18    .extern tlb_refill_handler
19    .extern cache_error_handler
20    .extern mips_irq_handle
21
22    /* 0x0 - TLB refill handler */
23    .global tlb_refill_exception
24    .type   tlb_refill_exception,@function
25ebase_start:
26tlb_refill_exception:
27    b   _general_exception_handler
28    nop
29
30    /* 0x080 - XTLB refill handler */
31    .org ebase_start + 0x080
32    b   _general_exception_handler
33    nop
34
35    /* 0x100 - Cache error handler */
36    .org ebase_start + 0x100
37    j   cache_error_handler
38    nop
39
40    /* 0x180 - Exception/Interrupt handler */
41    .global general_exception
42    .type   general_exception,@function
43    .org ebase_start + 0x180
44general_exception:
45    b   _general_exception_handler
46    nop
47
48    /* 0x200 - Special Exception Interrupt handler (when IV is set in CP0_CAUSE) */
49    .global irq_exception
50    .type   irq_exception,@function
51    .org ebase_start + 0x200
52irq_exception:
53    b   _general_exception_handler
54    nop
55
56    /* general exception handler */
57_general_exception_handler:
58    .set    noreorder
59    PTR_LA  k0, mips_irq_handle
60    jr  k0
61    nop
62    .set    reorder
63
64    /* interrupt handler */
65_irq_handler:
66    .set    noreorder
67    PTR_LA  k0, mips_irq_handle
68    jr  k0
69    nop
70    .set    reorder
71