1 /*
2  * Copyright (c) 2006-2021, RT-Thread Development Team
3  *
4  * SPDX-License-Identifier: Apache-2.0
5  *
6  * Change Logs:
7  * Date           Author       Notes
8  * 2019-12-04     Jiaxun Yang  Initial version
9  */
10 
11 #ifndef _MIPS_FPU_H_
12 #define _MIPS_FPU_H_
13 
14 #ifndef __ASSEMBLY__
15 
16 #include <mips_regs.h>
17 /**
18  * init hardware FPU
19  */
20 #ifdef RT_USING_FPU
rt_hw_fpu_init(void)21 rt_inline void rt_hw_fpu_init(void)
22 {
23     rt_uint32_t c0_status = 0;
24     rt_uint32_t c1_status = 0;
25 
26     /* Enable CU1 */
27     c0_status = read_c0_status();
28     c0_status |= (ST0_CU1 | ST0_FR);
29     write_c0_status(c0_status);
30 
31     /* FCSR Configs */
32     c1_status = read_c1_status();
33     c1_status |= (FPU_CSR_FS | FPU_CSR_FO | FPU_CSR_FN);    /* Set FS, FO, FN */
34     c1_status &= ~(FPU_CSR_ALL_E);                          /* Disable exception */
35     c1_status = (c1_status & (~FPU_CSR_RM)) | FPU_CSR_RN;   /* Set RN */
36     write_c1_status(c1_status);
37 
38     return ;
39 }
40 #else
rt_hw_fpu_init(void)41     rt_inline void rt_hw_fpu_init(void){} /* Do nothing */
42 #endif
43 
44 #endif
45 
46 #endif
47