1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2019-12-04 Jiaxun Yang Initial version
9 */
10
11 #ifndef _MIPS_REGS_H_
12 #define _MIPS_REGS_H_
13 #include <rtconfig.h>
14 #define REG_A0 4
15 #define REG_SP 29
16 #define REG_GP 28
17 #define REG_FP 30
18 #define REG_RA 31
19
20 #ifndef ARCH_MIPS64
21 #define zero $0 /* wired zero */
22 #define AT $1 /* assembler temp - uppercase because of ".set at" */
23 #define v0 $2 /* return value */
24 #define v1 $3
25 #define a0 $4 /* argument registers */
26 #define a1 $5
27 #define a2 $6
28 #define a3 $7
29 #define t0 $8 /* caller saved */
30 #define t1 $9
31 #define t2 $10
32 #define t3 $11
33 #define t4 $12
34 #define ta0 $12
35 #define t5 $13
36 #define ta1 $13
37 #define t6 $14
38 #define ta2 $14
39 #define t7 $15
40 #define ta3 $15
41 #define s0 $16 /* callee saved */
42 #define s1 $17
43 #define s2 $18
44 #define s3 $19
45 #define s4 $20
46 #define s5 $21
47 #define s6 $22
48 #define s7 $23
49 #define t8 $24 /* caller saved */
50 #define t9 $25
51 #define jp $25 /* PIC jump register */
52 #define k0 $26 /* kernel scratch */
53 #define k1 $27
54 #define gp $28 /* global pointer */
55 #define sp $29 /* stack pointer */
56 #define fp $30 /* frame pointer */
57 #define s8 $30 /* same like fp! */
58 #define ra $31 /* return address */
59
60 #else
61
62 #define zero $0 /* wired zero */
63 #define AT $at /* assembler temp - uppercase because of ".set at" */
64 #define v0 $2 /* return value - caller saved */
65 #define v1 $3
66 #define a0 $4 /* argument registers */
67 #define a1 $5
68 #define a2 $6
69 #define a3 $7
70 #define a4 $8 /* arg reg 64 bit; caller saved in 32 bit */
71 #define ta0 $8
72 #define a5 $9
73 #define ta1 $9
74 #define a6 $10
75 #define ta2 $10
76 #define a7 $11
77 #define ta3 $11
78 #define t0 $12 /* caller saved */
79 #define t1 $13
80 #define t2 $14
81 #define t3 $15
82 #define s0 $16 /* callee saved */
83 #define s1 $17
84 #define s2 $18
85 #define s3 $19
86 #define s4 $20
87 #define s5 $21
88 #define s6 $22
89 #define s7 $23
90 #define t8 $24 /* caller saved */
91 #define t9 $25 /* callee address for PIC/temp */
92 #define jp $25 /* PIC jump register */
93 #define k0 $26 /* kernel temporary */
94 #define k1 $27
95 #define gp $28 /* global pointer - caller saved for PIC */
96 #define sp $29 /* stack pointer */
97 #define fp $30 /* frame pointer */
98 #define s8 $30 /* callee saved */
99 #define ra $31 /* return address */
100
101 #endif
102
103 #define fv0 $f0 /* return value */
104 #define fv0f $f1
105 #define fv1 $f2
106 #define fv1f $f3
107 #define fa0 $f12 /* argument registers */
108 #define fa0f $f13
109 #define fa1 $f14
110 #define fa1f $f15
111 #define ft0 $f4 /* caller saved */
112 #define ft0f $f5
113 #define ft1 $f6
114 #define ft1f $f7
115 #define ft2 $f8
116 #define ft2f $f9
117 #define ft3 $f10
118 #define ft3f $f11
119 #define ft4 $f16
120 #define ft4f $f17
121 #define ft5 $f18
122 #define ft5f $f19
123 #define fs0 $f20 /* callee saved */
124 #define fs0f $f21
125 #define fs1 $f22
126 #define fs1f $f23
127 #define fs2 $f24
128 #define fs2f $f25
129 #define fs3 $f26
130 #define fs3f $f27
131 #define fs4 $f28
132 #define fs4f $f29
133 #define fs5 $f30
134 #define fs5f $f31
135
136 #define fcr31 $31 /* FPU status register */
137
138
139 /*
140 * The following macros are especially useful for __asm__
141 * inline assembler.
142 */
143 #ifndef __STR
144 #define __STR(x) #x
145 #endif
146 #ifndef STR
147 #define STR(x) __STR(x)
148 #endif
149
150 /*
151 * Configure language
152 */
153 #ifdef __ASSEMBLY__
154 #define _ULCAST_
155 #else
156 #define _ULCAST_ (unsigned long)
157 #endif
158
159 /*
160 * Coprocessor 0 register names
161 */
162 #define CP0_INDEX $0
163 #define CP0_RANDOM $1
164 #define CP0_ENTRYLO0 $2
165 #define CP0_ENTRYLO1 $3
166 #define CP0_CONF $3
167 #define CP0_CONTEXT $4
168 #define CP0_PAGEMASK $5
169 #define CP0_WIRED $6
170 #define CP0_INFO $7
171 #define CP0_BADVADDR $8
172 #define CP0_COUNT $9
173 #define CP0_ENTRYHI $10
174 #define CP0_COMPARE $11
175 #define CP0_STATUS $12
176 #define CP0_CAUSE $13
177 #define CP0_EPC $14
178 #define CP0_PRID $15
179 #define CP0_CONFIG $16
180 #define CP0_LLADDR $17
181 #define CP0_WATCHLO $18
182 #define CP0_WATCHHI $19
183 #define CP0_XCONTEXT $20
184 #define CP0_FRAMEMASK $21
185 #define CP0_DIAGNOSTIC $22
186 #define CP0_DEBUG $23
187 #define CP0_DEPC $24
188 #define CP0_PERFORMANCE $25
189 #define CP0_ECC $26
190 #define CP0_CACHEERR $27
191 #define CP0_TAGLO $28
192 #define CP0_TAGHI $29
193 #define CP0_ERROREPC $30
194 #define CP0_DESAVE $31
195
196 /*
197 * R4640/R4650 cp0 register names. These registers are listed
198 * here only for completeness; without MMU these CPUs are not useable
199 * by Linux. A future ELKS port might take make Linux run on them
200 * though ...
201 */
202 #define CP0_IBASE $0
203 #define CP0_IBOUND $1
204 #define CP0_DBASE $2
205 #define CP0_DBOUND $3
206 #define CP0_CALG $17
207 #define CP0_IWATCH $18
208 #define CP0_DWATCH $19
209
210 /*
211 * Coprocessor 0 Set 1 register names
212 */
213 #define CP0_S1_DERRADDR0 $26
214 #define CP0_S1_DERRADDR1 $27
215 #define CP0_S1_INTCONTROL $20
216
217 /*
218 * TX39 Series
219 */
220 #define CP0_TX39_CACHE $7
221
222 /*
223 * Coprocessor 1 (FPU) register names
224 */
225 #define CP1_REVISION $0
226 #define CP1_UFR $1
227 #define CP1_UNFR $4
228 #define CP1_FCCR $25
229 #define CP1_FEXR $26
230 #define CP1_FENR $28
231 #define CP1_STATUS $31
232
233
234 /*
235 * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
236 */
237 #define MIPS_FPIR_S (_ULCAST_(1) << 16)
238 #define MIPS_FPIR_D (_ULCAST_(1) << 17)
239 #define MIPS_FPIR_PS (_ULCAST_(1) << 18)
240 #define MIPS_FPIR_3D (_ULCAST_(1) << 19)
241 #define MIPS_FPIR_W (_ULCAST_(1) << 20)
242 #define MIPS_FPIR_L (_ULCAST_(1) << 21)
243 #define MIPS_FPIR_F64 (_ULCAST_(1) << 22)
244 #define MIPS_FPIR_HAS2008 (_ULCAST_(1) << 23)
245 #define MIPS_FPIR_UFRP (_ULCAST_(1) << 28)
246 #define MIPS_FPIR_FREP (_ULCAST_(1) << 29)
247
248 /*
249 * Bits in the MIPS32/64 coprocessor 1 (FPU) condition codes register.
250 */
251 #define MIPS_FCCR_CONDX_S 0
252 #define MIPS_FCCR_CONDX (_ULCAST_(255) << MIPS_FCCR_CONDX_S)
253 #define MIPS_FCCR_COND0_S 0
254 #define MIPS_FCCR_COND0 (_ULCAST_(1) << MIPS_FCCR_COND0_S)
255 #define MIPS_FCCR_COND1_S 1
256 #define MIPS_FCCR_COND1 (_ULCAST_(1) << MIPS_FCCR_COND1_S)
257 #define MIPS_FCCR_COND2_S 2
258 #define MIPS_FCCR_COND2 (_ULCAST_(1) << MIPS_FCCR_COND2_S)
259 #define MIPS_FCCR_COND3_S 3
260 #define MIPS_FCCR_COND3 (_ULCAST_(1) << MIPS_FCCR_COND3_S)
261 #define MIPS_FCCR_COND4_S 4
262 #define MIPS_FCCR_COND4 (_ULCAST_(1) << MIPS_FCCR_COND4_S)
263 #define MIPS_FCCR_COND5_S 5
264 #define MIPS_FCCR_COND5 (_ULCAST_(1) << MIPS_FCCR_COND5_S)
265 #define MIPS_FCCR_COND6_S 6
266 #define MIPS_FCCR_COND6 (_ULCAST_(1) << MIPS_FCCR_COND6_S)
267 #define MIPS_FCCR_COND7_S 7
268 #define MIPS_FCCR_COND7 (_ULCAST_(1) << MIPS_FCCR_COND7_S)
269
270 /*
271 * Bits in the MIPS32/64 coprocessor 1 (FPU) enables register.
272 */
273 #define MIPS_FENR_FS_S 2
274 #define MIPS_FENR_FS (_ULCAST_(1) << MIPS_FENR_FS_S)
275
276 /*
277 * FPU Status Register Values
278 */
279 #define FPU_CSR_COND_S 23 /* $fcc0 */
280 #define FPU_CSR_COND (_ULCAST_(1) << FPU_CSR_COND_S)
281
282 #define FPU_CSR_FS_S 24 /* flush denormalised results to 0 */
283 #define FPU_CSR_FS (_ULCAST_(1) << FPU_CSR_FS_S)
284
285 #define FPU_CSR_FO 0x00400000
286 #define FPU_CSR_FN 0x00200000
287
288 #define FPU_CSR_CONDX_S 25 /* $fcc[7:1] */
289 #define FPU_CSR_CONDX (_ULCAST_(127) << FPU_CSR_CONDX_S)
290 #define FPU_CSR_COND1_S 25 /* $fcc1 */
291 #define FPU_CSR_COND1 (_ULCAST_(1) << FPU_CSR_COND1_S)
292 #define FPU_CSR_COND2_S 26 /* $fcc2 */
293 #define FPU_CSR_COND2 (_ULCAST_(1) << FPU_CSR_COND2_S)
294 #define FPU_CSR_COND3_S 27 /* $fcc3 */
295 #define FPU_CSR_COND3 (_ULCAST_(1) << FPU_CSR_COND3_S)
296 #define FPU_CSR_COND4_S 28 /* $fcc4 */
297 #define FPU_CSR_COND4 (_ULCAST_(1) << FPU_CSR_COND4_S)
298 #define FPU_CSR_COND5_S 29 /* $fcc5 */
299 #define FPU_CSR_COND5 (_ULCAST_(1) << FPU_CSR_COND5_S)
300 #define FPU_CSR_COND6_S 30 /* $fcc6 */
301 #define FPU_CSR_COND6 (_ULCAST_(1) << FPU_CSR_COND6_S)
302 #define FPU_CSR_COND7_S 31 /* $fcc7 */
303 #define FPU_CSR_COND7 (_ULCAST_(1) << FPU_CSR_COND7_S)
304
305 /*
306 * Bits 22:20 of the FPU Status Register will be read as 0,
307 * and should be written as zero.
308 */
309 #define FPU_CSR_RSVD (_ULCAST_(7) << 20)
310
311 #define FPU_CSR_ABS2008 (_ULCAST_(1) << 19)
312 #define FPU_CSR_NAN2008 (_ULCAST_(1) << 18)
313
314 /*
315 * X the exception cause indicator
316 * E the exception enable
317 * S the sticky/flag bit
318 */
319 #define FPU_CSR_ALL_X 0x0003f000
320 #define FPU_CSR_UNI_X 0x00020000
321 #define FPU_CSR_INV_X 0x00010000
322 #define FPU_CSR_DIV_X 0x00008000
323 #define FPU_CSR_OVF_X 0x00004000
324 #define FPU_CSR_UDF_X 0x00002000
325 #define FPU_CSR_INE_X 0x00001000
326
327 #define FPU_CSR_ALL_E 0x00000f80
328 #define FPU_CSR_INV_E 0x00000800
329 #define FPU_CSR_DIV_E 0x00000400
330 #define FPU_CSR_OVF_E 0x00000200
331 #define FPU_CSR_UDF_E 0x00000100
332 #define FPU_CSR_INE_E 0x00000080
333
334 #define FPU_CSR_ALL_S 0x0000007c
335 #define FPU_CSR_INV_S 0x00000040
336 #define FPU_CSR_DIV_S 0x00000020
337 #define FPU_CSR_OVF_S 0x00000010
338 #define FPU_CSR_UDF_S 0x00000008
339 #define FPU_CSR_INE_S 0x00000004
340
341 /* Bits 0 and 1 of FPU Status Register specify the rounding mode */
342 #define FPU_CSR_RM 0x00000003
343 #define FPU_CSR_RN 0x0 /* nearest */
344 #define FPU_CSR_RZ 0x1 /* towards zero */
345 #define FPU_CSR_RU 0x2 /* towards +Infinity */
346 #define FPU_CSR_RD 0x3 /* towards -Infinity */
347
348 #define PM_4K 0x00000000
349 #define PM_16K 0x00006000
350 #define PM_64K 0x0001e000
351 #define PM_256K 0x0007e000
352 #define PM_1M 0x001fe000
353 #define PM_4M 0x007fe000
354 #define PM_16M 0x01ffe000
355 #define PM_64M 0x07ffe000
356 #define PM_256M 0x1fffe000
357
358
359 /*
360 * Values used for computation of new tlb entries
361 */
362 #define PL_4K 12
363 #define PL_16K 14
364 #define PL_64K 16
365 #define PL_256K 18
366 #define PL_1M 20
367 #define PL_4M 22
368 #define PL_16M 24
369 #define PL_64M 26
370 #define PL_256M 28
371
372 /*
373 * R4x00 interrupt enable / cause bits
374 */
375 #define IE_SW0 (_ULCAST_(1) << 8)
376 #define IE_SW1 (_ULCAST_(1) << 9)
377 #define IE_IRQ0 (_ULCAST_(1) << 10)
378 #define IE_IRQ1 (_ULCAST_(1) << 11)
379 #define IE_IRQ2 (_ULCAST_(1) << 12)
380 #define IE_IRQ3 (_ULCAST_(1) << 13)
381 #define IE_IRQ4 (_ULCAST_(1) << 14)
382 #define IE_IRQ5 (_ULCAST_(1) << 15)
383
384 /*
385 * R4x00 interrupt cause bits
386 */
387 #define C_SW0 (_ULCAST_(1) << 8)
388 #define C_SW1 (_ULCAST_(1) << 9)
389 #define C_IRQ0 (_ULCAST_(1) << 10)
390 #define C_IRQ1 (_ULCAST_(1) << 11)
391 #define C_IRQ2 (_ULCAST_(1) << 12)
392 #define C_IRQ3 (_ULCAST_(1) << 13)
393 #define C_IRQ4 (_ULCAST_(1) << 14)
394 #define C_IRQ5 (_ULCAST_(1) << 15)
395
396 /*
397 * Bitfields in the R4xx0 cp0 status register
398 */
399 #define ST0_IE 0x00000001
400 #define ST0_EXL 0x00000002
401 #define ST0_ERL 0x00000004
402 #define ST0_KSU 0x00000018
403 # define KSU_USER 0x00000010
404 # define KSU_SUPERVISOR 0x00000008
405 # define KSU_KERNEL 0x00000000
406 #define ST0_UX 0x00000020
407 #define ST0_SX 0x00000040
408 #define ST0_KX 0x00000080
409 #define ST0_DE 0x00010000
410 #define ST0_CE 0x00020000
411
412 /*
413 * Bitfields in the R[23]000 cp0 status register.
414 */
415 #define ST0_IEC 0x00000001
416 #define ST0_KUC 0x00000002
417 #define ST0_IEP 0x00000004
418 #define ST0_KUP 0x00000008
419 #define ST0_IEO 0x00000010
420 #define ST0_KUO 0x00000020
421 /* bits 6 & 7 are reserved on R[23]000 */
422 #define ST0_ISC 0x00010000
423 #define ST0_SWC 0x00020000
424 #define ST0_CM 0x00080000
425
426 /*
427 * Bits specific to the R4640/R4650
428 */
429 #define ST0_UM (_ULCAST_(1) << 4)
430 #define ST0_IL (_ULCAST_(1) << 23)
431 #define ST0_DL (_ULCAST_(1) << 24)
432
433
434 /*
435 * Status register bits available in all MIPS CPUs.
436 */
437 #define ST0_IM 0x0000ff00
438 #define STATUSB_IP0 8
439 #define STATUSF_IP0 (_ULCAST_(1) << 8)
440 #define STATUSB_IP1 9
441 #define STATUSF_IP1 (_ULCAST_(1) << 9)
442 #define STATUSB_IP2 10
443 #define STATUSF_IP2 (_ULCAST_(1) << 10)
444 #define STATUSB_IP3 11
445 #define STATUSF_IP3 (_ULCAST_(1) << 11)
446 #define STATUSB_IP4 12
447 #define STATUSF_IP4 (_ULCAST_(1) << 12)
448 #define STATUSB_IP5 13
449 #define STATUSF_IP5 (_ULCAST_(1) << 13)
450 #define STATUSB_IP6 14
451 #define STATUSF_IP6 (_ULCAST_(1) << 14)
452 #define STATUSB_IP7 15
453 #define STATUSF_IP7 (_ULCAST_(1) << 15)
454 #define STATUSB_IP8 0
455 #define STATUSF_IP8 (_ULCAST_(1) << 0)
456 #define STATUSB_IP9 1
457 #define STATUSF_IP9 (_ULCAST_(1) << 1)
458 #define STATUSB_IP10 2
459 #define STATUSF_IP10 (_ULCAST_(1) << 2)
460 #define STATUSB_IP11 3
461 #define STATUSF_IP11 (_ULCAST_(1) << 3)
462 #define STATUSB_IP12 4
463 #define STATUSF_IP12 (_ULCAST_(1) << 4)
464 #define STATUSB_IP13 5
465 #define STATUSF_IP13 (_ULCAST_(1) << 5)
466 #define STATUSB_IP14 6
467 #define STATUSF_IP14 (_ULCAST_(1) << 6)
468 #define STATUSB_IP15 7
469 #define STATUSF_IP15 (_ULCAST_(1) << 7)
470 #define ST0_CH 0x00040000
471 #define ST0_SR 0x00100000
472 #define ST0_TS 0x00200000
473 #define ST0_BEV 0x00400000
474 #define ST0_RE 0x02000000
475 #define ST0_FR 0x04000000
476 #define ST0_CU 0xf0000000
477 #define ST0_CU0 0x10000000
478 #define ST0_CU1 0x20000000
479 #define ST0_CU1_SHIFT 29
480 #define ST0_CU2 0x40000000
481 #define ST0_CU3 0x80000000
482 #define ST0_XX 0x80000000 /* MIPS IV naming */
483
484 /*
485 * Bitfields and bit numbers in the coprocessor 0 cause register.
486 *
487 * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
488 */
489 #define CAUSEB_EXCCODE 2
490 #define CAUSEF_EXCCODE (_ULCAST_(31) << 2)
491 #define CAUSEB_IP 8
492 #define CAUSEF_IP (_ULCAST_(255) << 8)
493 #define CAUSEB_IP0 8
494 #define CAUSEF_IP0 (_ULCAST_(1) << 8)
495 #define CAUSEB_IP1 9
496 #define CAUSEF_IP1 (_ULCAST_(1) << 9)
497 #define CAUSEB_IP2 10
498 #define CAUSEF_IP2 (_ULCAST_(1) << 10)
499 #define CAUSEB_IP3 11
500 #define CAUSEF_IP3 (_ULCAST_(1) << 11)
501 #define CAUSEB_IP4 12
502 #define CAUSEF_IP4 (_ULCAST_(1) << 12)
503 #define CAUSEB_IP5 13
504 #define CAUSEF_IP5 (_ULCAST_(1) << 13)
505 #define CAUSEB_IP6 14
506 #define CAUSEF_IP6 (_ULCAST_(1) << 14)
507 #define CAUSEB_IP7 15
508 #define CAUSEF_IP7 (_ULCAST_(1) << 15)
509 #define CAUSEB_IV 23
510 #define CAUSEF_IV (_ULCAST_(1) << 23)
511 #define CAUSEB_CE 28
512 #define CAUSEF_CE (_ULCAST_(3) << 28)
513 #define CAUSEB_BD 31
514 #define CAUSEF_BD (_ULCAST_(1) << 31)
515
516 /*
517 * Bits in the coprocessor 0 config register.
518 */
519 /* Generic bits. */
520 #define CONF_CM_CACHABLE_NO_WA 0
521 #define CONF_CM_CACHABLE_WA 1
522 #define CONF_CM_UNCACHED 2
523 #define CONF_CM_CACHABLE_NONCOHERENT 3
524 #define CONF_CM_CACHABLE_CE 4
525 #define CONF_CM_CACHABLE_COW 5
526 #define CONF_CM_CACHABLE_CUW 6
527 #define CONF_CM_CACHABLE_ACCELERATED 7
528 #define CONF_CM_CMASK 7
529 #define CONF_BE (_ULCAST_(1) << 15)
530
531 /* Bits common to various processors. */
532 #define CONF_CU (_ULCAST_(1) << 3)
533 #define CONF_DB (_ULCAST_(1) << 4)
534 #define CONF_IB (_ULCAST_(1) << 5)
535 #define CONF_DC (_ULCAST_(7) << 6)
536 #define CONF_IC (_ULCAST_(7) << 9)
537 #define CONF_EB (_ULCAST_(1) << 13)
538 #define CONF_EM (_ULCAST_(1) << 14)
539 #define CONF_SM (_ULCAST_(1) << 16)
540 #define CONF_SC (_ULCAST_(1) << 17)
541 #define CONF_EW (_ULCAST_(3) << 18)
542 #define CONF_EP (_ULCAST_(15)<< 24)
543 #define CONF_EC (_ULCAST_(7) << 28)
544 #define CONF_CM (_ULCAST_(1) << 31)
545
546 /* Bits specific to the R4xx0. */
547 #define R4K_CONF_SW (_ULCAST_(1) << 20)
548 #define R4K_CONF_SS (_ULCAST_(1) << 21)
549 #define R4K_CONF_SB (_ULCAST_(3) << 22)
550
551 /* Bits specific to the R5000. */
552 #define R5K_CONF_SE (_ULCAST_(1) << 12)
553 #define R5K_CONF_SS (_ULCAST_(3) << 20)
554
555 /* Bits specific to the R10000. */
556 #define R10K_CONF_DN (_ULCAST_(3) << 3)
557 #define R10K_CONF_CT (_ULCAST_(1) << 5)
558 #define R10K_CONF_PE (_ULCAST_(1) << 6)
559 #define R10K_CONF_PM (_ULCAST_(3) << 7)
560 #define R10K_CONF_EC (_ULCAST_(15)<< 9)
561 #define R10K_CONF_SB (_ULCAST_(1) << 13)
562 #define R10K_CONF_SK (_ULCAST_(1) << 14)
563 #define R10K_CONF_SS (_ULCAST_(7) << 16)
564 #define R10K_CONF_SC (_ULCAST_(7) << 19)
565 #define R10K_CONF_DC (_ULCAST_(7) << 26)
566 #define R10K_CONF_IC (_ULCAST_(7) << 29)
567
568 /* Bits specific to the VR41xx. */
569 #define VR41_CONF_CS (_ULCAST_(1) << 12)
570 #define VR41_CONF_M16 (_ULCAST_(1) << 20)
571 #define VR41_CONF_AD (_ULCAST_(1) << 23)
572
573 /* Bits specific to the R30xx. */
574 #define R30XX_CONF_FDM (_ULCAST_(1) << 19)
575 #define R30XX_CONF_REV (_ULCAST_(1) << 22)
576 #define R30XX_CONF_AC (_ULCAST_(1) << 23)
577 #define R30XX_CONF_RF (_ULCAST_(1) << 24)
578 #define R30XX_CONF_HALT (_ULCAST_(1) << 25)
579 #define R30XX_CONF_FPINT (_ULCAST_(7) << 26)
580 #define R30XX_CONF_DBR (_ULCAST_(1) << 29)
581 #define R30XX_CONF_SB (_ULCAST_(1) << 30)
582 #define R30XX_CONF_LOCK (_ULCAST_(1) << 31)
583
584 /* Bits specific to the TX49. */
585 #define TX49_CONF_DC (_ULCAST_(1) << 16)
586 #define TX49_CONF_IC (_ULCAST_(1) << 17) /* conflict with CONF_SC */
587 #define TX49_CONF_HALT (_ULCAST_(1) << 18)
588 #define TX49_CONF_CWFON (_ULCAST_(1) << 27)
589
590 /* Bits specific to the MIPS32/64 PRA. */
591 #define MIPS_CONF_MT (_ULCAST_(7) << 7)
592 #define MIPS_CONF_AR (_ULCAST_(7) << 10)
593 #define MIPS_CONF_AT (_ULCAST_(3) << 13)
594 #define MIPS_CONF_M (_ULCAST_(1) << 31)
595
596 /*
597 * R10000 performance counter definitions.
598 *
599 * FIXME: The R10000 performance counter opens a nice way to implement CPU
600 * time accounting with a precission of one cycle. I don't have
601 * R10000 silicon but just a manual, so ...
602 */
603
604 /*
605 * Events counted by counter #0
606 */
607 #define CE0_CYCLES 0
608 #define CE0_INSN_ISSUED 1
609 #define CE0_LPSC_ISSUED 2
610 #define CE0_S_ISSUED 3
611 #define CE0_SC_ISSUED 4
612 #define CE0_SC_FAILED 5
613 #define CE0_BRANCH_DECODED 6
614 #define CE0_QW_WB_SECONDARY 7
615 #define CE0_CORRECTED_ECC_ERRORS 8
616 #define CE0_ICACHE_MISSES 9
617 #define CE0_SCACHE_I_MISSES 10
618 #define CE0_SCACHE_I_WAY_MISSPREDICTED 11
619 #define CE0_EXT_INTERVENTIONS_REQ 12
620 #define CE0_EXT_INVALIDATE_REQ 13
621 #define CE0_VIRTUAL_COHERENCY_COND 14
622 #define CE0_INSN_GRADUATED 15
623
624 /*
625 * Events counted by counter #1
626 */
627 #define CE1_CYCLES 0
628 #define CE1_INSN_GRADUATED 1
629 #define CE1_LPSC_GRADUATED 2
630 #define CE1_S_GRADUATED 3
631 #define CE1_SC_GRADUATED 4
632 #define CE1_FP_INSN_GRADUATED 5
633 #define CE1_QW_WB_PRIMARY 6
634 #define CE1_TLB_REFILL 7
635 #define CE1_BRANCH_MISSPREDICTED 8
636 #define CE1_DCACHE_MISS 9
637 #define CE1_SCACHE_D_MISSES 10
638 #define CE1_SCACHE_D_WAY_MISSPREDICTED 11
639 #define CE1_EXT_INTERVENTION_HITS 12
640 #define CE1_EXT_INVALIDATE_REQ 13
641 #define CE1_SP_HINT_TO_CEXCL_SC_BLOCKS 14
642 #define CE1_SP_HINT_TO_SHARED_SC_BLOCKS 15
643
644 /*
645 * These flags define in which priviledge mode the counters count events
646 */
647 #define CEB_USER 8 /* Count events in user mode, EXL = ERL = 0 */
648 #define CEB_SUPERVISOR 4 /* Count events in supvervisor mode EXL = ERL = 0 */
649 #define CEB_KERNEL 2 /* Count events in kernel mode EXL = ERL = 0 */
650 #define CEB_EXL 1 /* Count events with EXL = 1, ERL = 0 */
651
652 #ifndef __ASSEMBLY__
653
654 #define CAUSE_EXCCODE(x) ((CAUSEF_EXCCODE & (x->cp0_cause)) >> CAUSEB_EXCCODE)
655 #define CAUSE_EPC(x) (x->cp0_epc + (((x->cp0_cause & CAUSEF_BD) >> CAUSEB_BD) << 2))
656
657 /*
658 * Functions to access the r10k performance counter and control registers
659 */
660 #define read_r10k_perf_cntr(counter) \
661 ({ unsigned int __res; \
662 __asm__ __volatile__( \
663 "mfpc\t%0, "STR(counter) \
664 : "=r" (__res)); \
665 __res;})
666
667 #define write_r10k_perf_cntr(counter,val) \
668 __asm__ __volatile__( \
669 "mtpc\t%0, "STR(counter) \
670 : : "r" (val));
671
672 #define read_r10k_perf_cntl(counter) \
673 ({ unsigned int __res; \
674 __asm__ __volatile__( \
675 "mfps\t%0, "STR(counter) \
676 : "=r" (__res)); \
677 __res;})
678
679 #define write_r10k_perf_cntl(counter,val) \
680 __asm__ __volatile__( \
681 "mtps\t%0, "STR(counter) \
682 : : "r" (val));
683
684 /*
685 * Macros to access the system control coprocessor
686 */
687
688 #define __read_32bit_c0_register(source, sel) \
689 ({ int __res; \
690 if (sel == 0) \
691 __asm__ __volatile__( \
692 "mfc0\t%0, " #source "\n\t" \
693 : "=r" (__res)); \
694 else \
695 __asm__ __volatile__( \
696 ".set\tmips32\n\t" \
697 "mfc0\t%0, " #source ", " #sel "\n\t" \
698 ".set\tmips0\n\t" \
699 : "=r" (__res)); \
700 __res; \
701 })
702
703 #define __read_64bit_c0_register(source, sel) \
704 ({ unsigned long __res; \
705 if (sel == 0) \
706 __asm__ __volatile__( \
707 ".set\tmips3\n\t" \
708 "dmfc0\t%0, " #source "\n\t" \
709 ".set\tmips0" \
710 : "=r" (__res)); \
711 else \
712 __asm__ __volatile__( \
713 ".set\tmips64\n\t" \
714 "dmfc0\t%0, " #source ", " #sel "\n\t" \
715 ".set\tmips0" \
716 : "=r" (__res)); \
717 __res; \
718 })
719
720 #define __write_32bit_c0_register(register, sel, value) \
721 do { \
722 if (sel == 0) \
723 __asm__ __volatile__( \
724 "mtc0\t%z0, " #register "\n\t" \
725 : : "Jr" (value)); \
726 else \
727 __asm__ __volatile__( \
728 ".set\tmips32\n\t" \
729 "mtc0\t%z0, " #register ", " #sel "\n\t" \
730 ".set\tmips0" \
731 : : "Jr" (value)); \
732 } while (0)
733
734 #define __write_64bit_c0_register(register, sel, value) \
735 do { \
736 if (sel == 0) \
737 __asm__ __volatile__( \
738 ".set\tmips3\n\t" \
739 "dmtc0\t%z0, " #register "\n\t" \
740 ".set\tmips0" \
741 : : "Jr" (value)); \
742 else \
743 __asm__ __volatile__( \
744 ".set\tmips64\n\t" \
745 "dmtc0\t%z0, " #register ", " #sel "\n\t" \
746 ".set\tmips0" \
747 : : "Jr" (value)); \
748 } while (0)
749
750 #define __read_ulong_c0_register(reg, sel) \
751 ((sizeof(unsigned long) == 4) ? \
752 __read_32bit_c0_register(reg, sel) : \
753 __read_64bit_c0_register(reg, sel))
754
755 #define __write_ulong_c0_register(reg, sel, val) \
756 do { \
757 if (sizeof(unsigned long) == 4) \
758 __write_32bit_c0_register(reg, sel, val); \
759 else \
760 __write_64bit_c0_register(reg, sel, val); \
761 } while (0)
762
763 /*
764 * These versions are only needed for systems with more than 38 bits of
765 * physical address space running the 32-bit kernel. That's none atm :-)
766 */
767 #define __read_64bit_c0_split(source, sel) \
768 ({ \
769 unsigned long long val; \
770 unsigned long flags; \
771 \
772 local_irq_save(flags); \
773 if (sel == 0) \
774 __asm__ __volatile__( \
775 ".set\tmips64\n\t" \
776 "dmfc0\t%M0, " #source "\n\t" \
777 "dsll\t%L0, %M0, 32\n\t" \
778 "dsrl\t%M0, %M0, 32\n\t" \
779 "dsrl\t%L0, %L0, 32\n\t" \
780 ".set\tmips0" \
781 : "=r" (val)); \
782 else \
783 __asm__ __volatile__( \
784 ".set\tmips64\n\t" \
785 "dmfc0\t%M0, " #source ", " #sel "\n\t" \
786 "dsll\t%L0, %M0, 32\n\t" \
787 "dsrl\t%M0, %M0, 32\n\t" \
788 "dsrl\t%L0, %L0, 32\n\t" \
789 ".set\tmips0" \
790 : "=r" (val)); \
791 local_irq_restore(flags); \
792 \
793 val; \
794 })
795
796 #define __write_64bit_c0_split(source, sel, val) \
797 do { \
798 unsigned long flags; \
799 \
800 local_irq_save(flags); \
801 if (sel == 0) \
802 __asm__ __volatile__( \
803 ".set\tmips64\n\t" \
804 "dsll\t%L0, %L0, 32\n\t" \
805 "dsrl\t%L0, %L0, 32\n\t" \
806 "dsll\t%M0, %M0, 32\n\t" \
807 "or\t%L0, %L0, %M0\n\t" \
808 "dmtc0\t%L0, " #source "\n\t" \
809 ".set\tmips0" \
810 : : "r" (val)); \
811 else \
812 __asm__ __volatile__( \
813 ".set\tmips64\n\t" \
814 "dsll\t%L0, %L0, 32\n\t" \
815 "dsrl\t%L0, %L0, 32\n\t" \
816 "dsll\t%M0, %M0, 32\n\t" \
817 "or\t%L0, %L0, %M0\n\t" \
818 "dmtc0\t%L0, " #source ", " #sel "\n\t" \
819 ".set\tmips0" \
820 : : "r" (val)); \
821 local_irq_restore(flags); \
822 } while (0)
823
824 #define read_c0_index() __read_32bit_c0_register($0, 0)
825 #define write_c0_index(val) __write_32bit_c0_register($0, 0, val)
826
827 #define read_c0_entrylo0() __read_ulong_c0_register($2, 0)
828 #define write_c0_entrylo0(val) __write_ulong_c0_register($2, 0, val)
829
830 #define read_c0_entrylo1() __read_ulong_c0_register($3, 0)
831 #define write_c0_entrylo1(val) __write_ulong_c0_register($3, 0, val)
832
833 #define read_c0_conf() __read_32bit_c0_register($3, 0)
834 #define write_c0_conf(val) __write_32bit_c0_register($3, 0, val)
835
836 #define read_c0_context() __read_ulong_c0_register($4, 0)
837 #define write_c0_context(val) __write_ulong_c0_register($4, 0, val)
838
839 #define read_c0_pagemask() __read_32bit_c0_register($5, 0)
840 #define write_c0_pagemask(val) __write_32bit_c0_register($5, 0, val)
841
842 #define read_c0_wired() __read_32bit_c0_register($6, 0)
843 #define write_c0_wired(val) __write_32bit_c0_register($6, 0, val)
844
845 #define read_c0_info() __read_32bit_c0_register($7, 0)
846
847 #define read_c0_cache() __read_32bit_c0_register($7, 0) /* TX39xx */
848 #define write_c0_cache(val) __write_32bit_c0_register($7, 0, val)
849
850 #define read_c0_count() __read_32bit_c0_register($9, 0)
851 #define write_c0_count(val) __write_32bit_c0_register($9, 0, val)
852
853 #define read_c0_entryhi() __read_ulong_c0_register($10, 0)
854 #define write_c0_entryhi(val) __write_ulong_c0_register($10, 0, val)
855
856 #define read_c0_compare() __read_32bit_c0_register($11, 0)
857 #define write_c0_compare(val) __write_32bit_c0_register($11, 0, val)
858
859 #define read_c0_status() __read_32bit_c0_register($12, 0)
860 #define write_c0_status(val) __write_32bit_c0_register($12, 0, val)
861
862 #define read_c0_cause() __read_32bit_c0_register($13, 0)
863 #define write_c0_cause(val) __write_32bit_c0_register($13, 0, val)
864
865 #define read_c0_prid() __read_32bit_c0_register($15, 0)
866
867 #define read_c0_ebase() __read_32bit_c0_register($15, 1)
868 #define write_c0_ebase(val) __write_32bit_c0_register($15, 1, val)
869
870 #define read_c0_config() __read_32bit_c0_register($16, 0)
871 #define read_c0_config1() __read_32bit_c0_register($16, 1)
872 #define read_c0_config2() __read_32bit_c0_register($16, 2)
873 #define read_c0_config3() __read_32bit_c0_register($16, 3)
874 #define write_c0_config(val) __write_32bit_c0_register($16, 0, val)
875 #define write_c0_config1(val) __write_32bit_c0_register($16, 1, val)
876 #define write_c0_config2(val) __write_32bit_c0_register($16, 2, val)
877 #define write_c0_config3(val) __write_32bit_c0_register($16, 3, val)
878
879 /*
880 * The WatchLo register. There may be upto 8 of them.
881 */
882 #define read_c0_watchlo0() __read_ulong_c0_register($18, 0)
883 #define read_c0_watchlo1() __read_ulong_c0_register($18, 1)
884 #define read_c0_watchlo2() __read_ulong_c0_register($18, 2)
885 #define read_c0_watchlo3() __read_ulong_c0_register($18, 3)
886 #define read_c0_watchlo4() __read_ulong_c0_register($18, 4)
887 #define read_c0_watchlo5() __read_ulong_c0_register($18, 5)
888 #define read_c0_watchlo6() __read_ulong_c0_register($18, 6)
889 #define read_c0_watchlo7() __read_ulong_c0_register($18, 7)
890 #define write_c0_watchlo0(val) __write_ulong_c0_register($18, 0, val)
891 #define write_c0_watchlo1(val) __write_ulong_c0_register($18, 1, val)
892 #define write_c0_watchlo2(val) __write_ulong_c0_register($18, 2, val)
893 #define write_c0_watchlo3(val) __write_ulong_c0_register($18, 3, val)
894 #define write_c0_watchlo4(val) __write_ulong_c0_register($18, 4, val)
895 #define write_c0_watchlo5(val) __write_ulong_c0_register($18, 5, val)
896 #define write_c0_watchlo6(val) __write_ulong_c0_register($18, 6, val)
897 #define write_c0_watchlo7(val) __write_ulong_c0_register($18, 7, val)
898
899 /*
900 * The WatchHi register. There may be upto 8 of them.
901 */
902 #define read_c0_watchhi0() __read_32bit_c0_register($19, 0)
903 #define read_c0_watchhi1() __read_32bit_c0_register($19, 1)
904 #define read_c0_watchhi2() __read_32bit_c0_register($19, 2)
905 #define read_c0_watchhi3() __read_32bit_c0_register($19, 3)
906 #define read_c0_watchhi4() __read_32bit_c0_register($19, 4)
907 #define read_c0_watchhi5() __read_32bit_c0_register($19, 5)
908 #define read_c0_watchhi6() __read_32bit_c0_register($19, 6)
909 #define read_c0_watchhi7() __read_32bit_c0_register($19, 7)
910
911 #define write_c0_watchhi0(val) __write_32bit_c0_register($19, 0, val)
912 #define write_c0_watchhi1(val) __write_32bit_c0_register($19, 1, val)
913 #define write_c0_watchhi2(val) __write_32bit_c0_register($19, 2, val)
914 #define write_c0_watchhi3(val) __write_32bit_c0_register($19, 3, val)
915 #define write_c0_watchhi4(val) __write_32bit_c0_register($19, 4, val)
916 #define write_c0_watchhi5(val) __write_32bit_c0_register($19, 5, val)
917 #define write_c0_watchhi6(val) __write_32bit_c0_register($19, 6, val)
918 #define write_c0_watchhi7(val) __write_32bit_c0_register($19, 7, val)
919
920 #define read_c0_xcontext() __read_ulong_c0_register($20, 0)
921 #define write_c0_xcontext(val) __write_ulong_c0_register($20, 0, val)
922
923 #define read_c0_intcontrol() __read_32bit_c0_register($20, 1)
924 #define write_c0_intcontrol(val) __write_32bit_c0_register($20, 1, val)
925
926 #define read_c0_framemask() __read_32bit_c0_register($21, 0)
927 #define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
928
929 #define read_c0_debug() __read_32bit_c0_register($23, 0)
930 #define write_c0_debug(val) __write_32bit_c0_register($23, 0, val)
931
932 #define read_c0_depc() __read_ulong_c0_register($24, 0)
933 #define write_c0_depc(val) __write_ulong_c0_register($24, 0, val)
934
935 #define read_c0_ecc() __read_32bit_c0_register($26, 0)
936 #define write_c0_ecc(val) __write_32bit_c0_register($26, 0, val)
937
938 #define read_c0_derraddr0() __read_ulong_c0_register($26, 1)
939 #define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
940
941 #define read_c0_cacheerr() __read_32bit_c0_register($27, 0)
942
943 #define read_c0_derraddr1() __read_ulong_c0_register($27, 1)
944 #define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
945
946 #define read_c0_taglo() __read_32bit_c0_register($28, 0)
947 #define write_c0_taglo(val) __write_32bit_c0_register($28, 0, val)
948
949 #define read_c0_taghi() __read_32bit_c0_register($29, 0)
950 #define write_c0_taghi(val) __write_32bit_c0_register($29, 0, val)
951
952 #define read_c0_errorepc() __read_ulong_c0_register($30, 0)
953 #define write_c0_errorepc(val) __write_ulong_c0_register($30, 0, val)
954
955 #define read_c0_epc() __read_ulong_c0_register($14, 0)
956 #define write_c0_epc(val) __write_ulong_c0_register($14, 0, val)
957
958 #if 1
959 /*
960 * Macros to access the system control coprocessor
961 */
962 #define read_32bit_cp0_register(source) \
963 ({ int __res; \
964 __asm__ __volatile__( \
965 ".set\tpush\n\t" \
966 ".set\treorder\n\t" \
967 "mfc0\t%0,"STR(source)"\n\t" \
968 ".set\tpop" \
969 : "=r" (__res)); \
970 __res;})
971
972 #define read_32bit_cp0_set1_register(source) \
973 ({ int __res; \
974 __asm__ __volatile__( \
975 ".set\tpush\n\t" \
976 ".set\treorder\n\t" \
977 "cfc0\t%0,"STR(source)"\n\t" \
978 ".set\tpop" \
979 : "=r" (__res)); \
980 __res;})
981
982 /*
983 * For now use this only with interrupts disabled!
984 */
985 #define read_64bit_cp0_register(source) \
986 ({ int __res; \
987 __asm__ __volatile__( \
988 ".set\tmips3\n\t" \
989 "dmfc0\t%0,"STR(source)"\n\t" \
990 ".set\tmips0" \
991 : "=r" (__res)); \
992 __res;})
993
994 #define write_32bit_cp0_register(register,value) \
995 __asm__ __volatile__( \
996 "mtc0\t%0,"STR(register)"\n\t" \
997 "nop" \
998 : : "r" (value));
999
1000 #define write_32bit_cp0_set1_register(register,value) \
1001 __asm__ __volatile__( \
1002 "ctc0\t%0,$"STR(register)"\n\t" \
1003 "nop" \
1004 : : "r" (value));
1005
1006 #define write_64bit_cp0_register(register,value) \
1007 __asm__ __volatile__( \
1008 ".set\tmips3\n\t" \
1009 "dmtc0\t%0,"STR(register)"\n\t" \
1010 ".set\tmips0" \
1011 : : "r" (value))
1012
1013 /*
1014 * This should be changed when we get a compiler that support the MIPS32 ISA.
1015 */
1016 #define read_mips32_cp0_config1() \
1017 ({ int __res; \
1018 __asm__ __volatile__( \
1019 ".set\tnoreorder\n\t" \
1020 ".set\tnoat\n\t" \
1021 "#.set\tmips64\n\t" \
1022 "#mfc0\t$1, $16, 1\n\t" \
1023 "#.set\tmips0\n\t" \
1024 ".word\t0x40018001\n\t" \
1025 "move\t%0,$1\n\t" \
1026 ".set\tat\n\t" \
1027 ".set\treorder" \
1028 :"=r" (__res)); \
1029 __res;})
1030
1031 #endif
1032 /*
1033 * Macros to access the floating point coprocessor control registers
1034 */
1035 #define read_32bit_cp1_register(source) \
1036 ({ int __res; \
1037 __asm__ __volatile__( \
1038 ".set\tpush\n\t" \
1039 ".set\treorder\n\t" \
1040 "cfc1\t%0,$"STR(source)"\n\t" \
1041 ".set\tpop" \
1042 : "=r" (__res)); \
1043 __res;})
1044
1045 #define write_32bit_cp1_register(register,value) \
1046 __asm__ __volatile__( \
1047 "ctc1\t%0,$"STR(register)"\n\t" \
1048 "nop" \
1049 : : "r" (value));
1050
1051 /* TLB operations. */
tlb_probe(void)1052 static inline void tlb_probe(void)
1053 {
1054 __asm__ __volatile__(
1055 ".set noreorder\n\t"
1056 "tlbp\n\t"
1057 ".set reorder");
1058 }
1059
tlb_read(void)1060 static inline void tlb_read(void)
1061 {
1062 __asm__ __volatile__(
1063 ".set noreorder\n\t"
1064 "tlbr\n\t"
1065 ".set reorder");
1066 }
1067
tlb_write_indexed(void)1068 static inline void tlb_write_indexed(void)
1069 {
1070 __asm__ __volatile__(
1071 ".set noreorder\n\t"
1072 "tlbwi\n\t"
1073 ".set reorder");
1074 }
1075
tlb_write_random(void)1076 static inline void tlb_write_random(void)
1077 {
1078 __asm__ __volatile__(
1079 ".set noreorder\n\t"
1080 "tlbwr\n\t"
1081 ".set reorder");
1082 }
1083
1084 /*
1085 * Manipulate bits in a c0 register.
1086 */
1087 #define __BUILD_SET_C0(name,register) \
1088 static inline unsigned int \
1089 set_c0_##name(unsigned int set) \
1090 { \
1091 unsigned int res; \
1092 \
1093 res = read_c0_##name(); \
1094 res |= set; \
1095 write_c0_##name(res); \
1096 \
1097 return res; \
1098 } \
1099 \
1100 static inline unsigned int \
1101 clear_c0_##name(unsigned int clear) \
1102 { \
1103 unsigned int res; \
1104 \
1105 res = read_c0_##name(); \
1106 res &= ~clear; \
1107 write_c0_##name(res); \
1108 \
1109 return res; \
1110 } \
1111 \
1112 static inline unsigned int \
1113 change_c0_##name(unsigned int change, unsigned int new) \
1114 { \
1115 unsigned int res; \
1116 \
1117 res = read_c0_##name(); \
1118 res &= ~change; \
1119 res |= (new & change); \
1120 write_c0_##name(res); \
1121 \
1122 return res; \
1123 }
1124
1125 __BUILD_SET_C0(status,CP0_STATUS)
1126 __BUILD_SET_C0(cause,CP0_CAUSE)
1127 __BUILD_SET_C0(config,CP0_CONFIG)
1128
1129 #define set_cp0_status(x) set_c0_status(x)
1130 #define set_cp0_cause(x) set_c0_cause(x)
1131 #define set_cp0_config(x) set_c0_config(x)
1132
1133 #define read_c1_status() read_32bit_cp1_register(31)
1134 #define write_c1_status(x) write_32bit_cp1_register(31, x)
1135
1136 #define readb(reg) (*((volatile unsigned char *) (reg)))
1137 #define readw(reg) (*((volatile unsigned short *) (reg)))
1138 #define readl(reg) (*((volatile unsigned int *) (reg)))
1139
1140 #define writeb(data, reg) ((*((volatile unsigned char *)(reg))) = (unsigned char)(data))
1141 #define writew(data, reg) ((*((volatile unsigned short *)(reg))) = (unsigned short)(data))
1142 #define writel(data, reg) ((*((volatile unsigned int *)(reg))) = (unsigned int)(data))
1143
1144 #endif /* !__ASSEMBLY__ */
1145
1146 #endif /* _MIPS_REGS_H_ */
1147