1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2019-12-04 Jiaxun Yang Initial version 9 */ 10 11 #include <rtthread.h> 12 13 #include "mips.h" 14 15 register rt_uint32_t $GP __asm__ ("$28"); 16 rt_hw_stack_init(void * tentry,void * parameter,rt_uint8_t * stack_addr,void * texit)17rt_uint8_t *rt_hw_stack_init(void *tentry, void *parameter, rt_uint8_t *stack_addr, void *texit) 18 { 19 static rt_ubase_t wSR=0; 20 static rt_ubase_t wGP; 21 rt_uint8_t *stk; 22 23 struct pt_regs *pt; 24 25 rt_uint32_t i; 26 27 /* Get stack aligned */ 28 stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stack_addr, 8); 29 stk -= sizeof(struct pt_regs); 30 pt = (struct pt_regs*)stk; 31 32 #ifndef ARCH_MIPS64 33 for (i = 0; i < 8; ++i) 34 { 35 pt->pad0[i] = 0xdeadbeef; 36 } 37 #endif 38 /* Fill Stack register numbers */ 39 for (i = 0; i < 32; ++i) 40 { 41 pt->regs[i] = 0xdeadbeef; 42 } 43 44 pt->regs[REG_SP] = (rt_ubase_t)stk; 45 pt->regs[REG_A0] = (rt_ubase_t)parameter; 46 pt->regs[REG_GP] = (rt_ubase_t)$GP; 47 pt->regs[REG_FP] = (rt_ubase_t)0x0; 48 pt->regs[REG_RA] = (rt_ubase_t)texit; 49 50 pt->hi = 0x0; 51 pt->lo = 0x0; 52 pt->cp0_status = (ST0_IE | ST0_CU0 | ST0_IM); 53 #ifdef RT_USING_FPU 54 pt->cp0_status |= (ST0_CU1 | ST0_FR); 55 #endif 56 pt->cp0_cause = read_c0_cause(); 57 pt->cp0_epc = (rt_ubase_t)tentry; 58 pt->cp0_badvaddr = 0x0; 59 60 return stk; 61 } 62