1 /*
2 * Copyright (c) 2006-2021, RT-Thread Development Team
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 * Change Logs:
7 * Date Author Notes
8 * 2010-05-27 swkyer first version
9 */
10 #include <rtthread.h>
11 #include <mips.h>
12
13 mips32_core_cfg_t g_mips_core =
14 {
15 16, /* icache_line_size */
16 256, /* icache_lines_per_way */
17 4, /* icache_ways */
18 16, /* dcache_line_size */
19 256, /* dcache_lines_per_way */
20 4, /* dcache_ways */
21 16, /* max_tlb_entries */
22 };
23
m_pow(rt_uint16_t b,rt_uint16_t n)24 static rt_uint16_t m_pow(rt_uint16_t b, rt_uint16_t n)
25 {
26 rt_uint16_t rets = 1;
27
28 while (n--)
29 rets *= b;
30
31 return rets;
32 }
33
m_log2(rt_uint16_t b)34 static rt_uint16_t m_log2(rt_uint16_t b)
35 {
36 rt_uint16_t rets = 0;
37
38 while (b != 1)
39 {
40 b /= 2;
41 rets++;
42 }
43
44 return rets;
45 }
46
47 /**
48 * read core attribute
49 */
mips32_cfg_init(void)50 void mips32_cfg_init(void)
51 {
52 rt_uint16_t val;
53 rt_uint32_t cp0_config1;
54
55 cp0_config1 = read_c0_config();
56 if (cp0_config1 & 0x80000000)
57 {
58 cp0_config1 = read_c0_config1();
59
60 val = (cp0_config1 & (7<<22))>>22;
61 g_mips_core.icache_lines_per_way = 64 * m_pow(2, val);
62 val = (cp0_config1 & (7<<19))>>19;
63 g_mips_core.icache_line_size = 2 * m_pow(2, val);
64 val = (cp0_config1 & (7<<16))>>16;
65 g_mips_core.icache_ways = val + 1;
66
67 val = (cp0_config1 & (7<<13))>>13;
68 g_mips_core.dcache_lines_per_way = 64 * m_pow(2, val);
69 val = (cp0_config1 & (7<<10))>>10;
70 g_mips_core.dcache_line_size = 2 * m_pow(2, val);
71 val = (cp0_config1 & (7<<7))>>7;
72 g_mips_core.dcache_ways = val + 1;
73
74 val = (cp0_config1 & (0x3F<<25))>>25;
75 g_mips_core.max_tlb_entries = val + 1;
76 }
77 }
78