1 /*
2 * Copyright (c) 2019-2020, Xim
3 *
4 * SPDX-License-Identifier: Apache-2.0
5 *
6 */
7 #ifndef ARCH_IO_H
8 #define ARCH_IO_H
9 #include <rtthread.h>
10 #define RISCV_FENCE(p, s) \
11 __asm__ __volatile__ ("fence " #p "," #s : : : "memory")
12
13 /* These barriers need to enforce ordering on both devices or memory. */
14 #define mb() RISCV_FENCE(iorw,iorw)
15 #define rmb() RISCV_FENCE(ir,ir)
16 #define wmb() RISCV_FENCE(ow,ow)
17
18 #define __arch_getl(a) (*(unsigned int *)(a))
19 #define __arch_putl(v, a) (*(unsigned int *)(a) = (v))
20
21 #define dmb() mb()
22 #define __iormb() rmb()
23 #define __iowmb() wmb()
24
writel(uint32_t val,volatile void * addr)25 static inline void writel(uint32_t val, volatile void *addr)
26 {
27 __iowmb();
28 __arch_putl(val, addr);
29 }
30
readl(const volatile void * addr)31 static inline uint32_t readl(const volatile void *addr)
32 {
33 uint32_t val;
34
35 val = __arch_getl(addr);
36 __iormb();
37 return val;
38 }
39
write_reg(uint32_t val,volatile void * addr,unsigned offset)40 static inline void write_reg(
41 uint32_t val, volatile void *addr, unsigned offset)
42 {
43 writel(val, (void *)((rt_size_t)addr + offset));
44 }
45
read_reg(const volatile void * addr,unsigned offset)46 static inline uint32_t read_reg(
47 const volatile void *addr, unsigned offset)
48 {
49 return readl((void *)((rt_size_t)addr + offset));
50 }
51
52 #endif // ARCH_IO_H
53