1 /* 2 * Copyright (c) 2006-2021, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2021-01-30 lizhirui first version 9 * 2021-11-18 JasonHu add fpu member 10 * 2022-10-22 Shell Support kernel mode RVV 11 */ 12 13 #ifndef __STACK_H__ 14 #define __STACK_H__ 15 16 #include "stackframe.h" 17 18 #include <rtthread.h> 19 20 typedef struct rt_hw_switch_frame 21 { 22 uint64_t regs[RT_HW_SWITCH_CONTEXT_SIZE]; 23 } *rt_hw_switch_frame_t; 24 25 26 struct rt_hw_stack_frame 27 { 28 rt_ubase_t epc; /* epc - epc - program counter */ 29 rt_ubase_t ra; /* x1 - ra - return address for jumps */ 30 rt_ubase_t sstatus; /* - supervisor status register */ 31 rt_ubase_t gp; /* x3 - gp - global pointer */ 32 rt_ubase_t tp; /* x4 - tp - thread pointer */ 33 rt_ubase_t t0; /* x5 - t0 - temporary register 0 */ 34 rt_ubase_t t1; /* x6 - t1 - temporary register 1 */ 35 rt_ubase_t t2; /* x7 - t2 - temporary register 2 */ 36 rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */ 37 rt_ubase_t s1; /* x9 - s1 - saved register 1 */ 38 rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */ 39 rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */ 40 rt_ubase_t a2; /* x12 - a2 - function argument 2 */ 41 rt_ubase_t a3; /* x13 - a3 - function argument 3 */ 42 rt_ubase_t a4; /* x14 - a4 - function argument 4 */ 43 rt_ubase_t a5; /* x15 - a5 - function argument 5 */ 44 rt_ubase_t a6; /* x16 - a6 - function argument 6 */ 45 rt_ubase_t a7; /* x17 - s7 - function argument 7 */ 46 rt_ubase_t s2; /* x18 - s2 - saved register 2 */ 47 rt_ubase_t s3; /* x19 - s3 - saved register 3 */ 48 rt_ubase_t s4; /* x20 - s4 - saved register 4 */ 49 rt_ubase_t s5; /* x21 - s5 - saved register 5 */ 50 rt_ubase_t s6; /* x22 - s6 - saved register 6 */ 51 rt_ubase_t s7; /* x23 - s7 - saved register 7 */ 52 rt_ubase_t s8; /* x24 - s8 - saved register 8 */ 53 rt_ubase_t s9; /* x25 - s9 - saved register 9 */ 54 rt_ubase_t s10; /* x26 - s10 - saved register 10 */ 55 rt_ubase_t s11; /* x27 - s11 - saved register 11 */ 56 rt_ubase_t t3; /* x28 - t3 - temporary register 3 */ 57 rt_ubase_t t4; /* x29 - t4 - temporary register 4 */ 58 rt_ubase_t t5; /* x30 - t5 - temporary register 5 */ 59 rt_ubase_t t6; /* x31 - t6 - temporary register 6 */ 60 rt_ubase_t user_sp_exc_stack; /* sscratch - user mode sp/exception stack */ 61 rt_ubase_t __padding; /* align to 16bytes */ 62 #ifdef ARCH_RISCV_FPU 63 rt_ubase_t f[CTX_FPU_REG_NR]; /* f0~f31 */ 64 #endif /* ARCH_RISCV_FPU */ 65 #ifdef ARCH_RISCV_VECTOR 66 rt_ubase_t v[CTX_VECTOR_REG_NR]; 67 #endif /* ARCH_RISCV_VECTOR */ 68 }; 69 70 #endif 71