1 /* 2 * Copyright (c) 2006-2023, RT-Thread Development Team 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Change Logs: 7 * Date Author Notes 8 * 2021-10-19 JasonHu first version 9 * 2023-04-22 flyingcys add C906_PLIC_PHY_ADDR macro judge 10 */ 11 12 #ifndef __RISCV64_PLIC_H__ 13 #define __RISCV64_PLIC_H__ 14 15 #include <interrupt.h> 16 17 #ifndef C906_PLIC_PHY_ADDR 18 #define C906_PLIC_PHY_ADDR (0x10000000) 19 #endif 20 #define C906_PLIC_NR_EXT_IRQS (IRQ_MAX_NR) 21 #define C906_NR_CPUS (NR_CPUS) 22 23 /* M and S mode context. */ 24 #define C906_NR_CONTEXT (2) 25 26 #define MAX_DEVICES 1024 27 #define MAX_CONTEXTS 15872 28 29 /* 30 * Each interrupt source has a priority register associated with it. 31 * We always hardwire it to one in Linux. 32 */ 33 #define PRIORITY_BASE 0 34 #define PRIORITY_PER_ID 4 35 36 /* 37 * Each hart context has a vector of interrupt enable bits associated with it. 38 * There's one bit for each interrupt source. 39 */ 40 #define ENABLE_BASE 0x2000 41 #define ENABLE_PER_HART 0x80 42 43 /* 44 * Each hart context has a set of control registers associated with it. Right 45 * now there's only two: a source priority threshold over which the hart will 46 * take an interrupt, and a register to claim interrupts. 47 */ 48 #define CONTEXT_BASE 0x200000 49 #define CONTEXT_PER_HART 0x1000 50 #define CONTEXT_THRESHOLD 0x00 51 #define CONTEXT_CLAIM 0x04 52 53 void plic_init(void); 54 void plic_enable_irq(int irqno); 55 void plic_disable_irq(int irqno); 56 // tell PLIC that we've served this IRQ 57 void plic_complete(int irq); 58 void plic_handle_irq(void); 59 60 #endif 61