1;
2; Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
3;
4; SPDX-License-Identifier: Apache-2.0
5;
6; Change Logs:
7; Date           Author       Notes
8; 2021-11-16     Dystopia     the first version
9;
10
11;-----------------------------------------------------------
12;                       extern variable
13;-----------------------------------------------------------
14    .ref rt_system_stack_top
15
16;-----------------------------------------------------------
17;                     macro definition
18;-----------------------------------------------------------
19SAVE_ALL    .macro  __rp, __tsr
20    STW .D2T2   B0,*SP--[2]             ; save original B0
21    MVKL    .S2 rt_system_stack_top,B0
22    MVKH    .S2 rt_system_stack_top,B0
23    LDW .D2T2   *B0,B1                  ; system stack
24
25    NOP 3
26    STW .D2T2   B1,*+SP[1]              ; save original B1
27    XOR .D2 SP,B1,B0                    ; check current stack types
28    LDW .D2T2   *+SP[1],B1              ; restore B0/B1
29    LDW .D2T2   *++SP[2],B0
30    SHR .S2 B0,12,B0                    ; 0 if already using system stack
31 [B0]   STDW    .D2T2   SP:DP,*--B1[1]  ; thread: save thread sp/dp system stack
32 [B0]   MV  .S2 B1,SP                   ; and switch to system stack
33||[!B0] STDW    .D2T2   SP:DP,*--SP[1]  ; kernel: nest interrupt save(not support)
34
35    SUBAW   .D2 SP,2,SP
36
37    ADD .D1X    SP,-8,A15
38 || STDW    .D2T1   A15:A14,*SP--[16]   ; save A15:A14
39
40    STDW    .D2T2   B13:B12,*SP--[1]
41 || STDW    .D1T1   A13:A12,*A15--[1]
42 || MVC .S2 __rp,B13
43    STDW    .D2T2   B11:B10,*SP--[1]
44 || STDW    .D1T1   A11:A10,*A15--[1]
45 || MVC .S2 CSR,B12
46
47    STDW    .D2T2   B9:B8,*SP--[1]
48 || STDW    .D1T1   A9:A8,*A15--[1]
49 || MVC .S2 RILC,B11
50    STDW    .D2T2   B7:B6,*SP--[1]
51 || STDW    .D1T1   A7:A6,*A15--[1]
52 || MVC .S2 ILC,B10
53    STDW    .D2T2   B5:B4,*SP--[1]
54 || STDW    .D1T1   A5:A4,*A15--[1]
55    STDW    .D2T2   B3:B2,*SP--[1]
56 || STDW    .D1T1   A3:A2,*A15--[1]
57 || MVC .S2 __tsr,B5
58    STDW    .D2T2   B1:B0,*SP--[1]
59 || STDW    .D1T1   A1:A0,*A15--[1]
60 || MV  .S1X    B5,A5
61
62    STDW    .D2T2   B31:B30,*SP--[1]
63 || STDW    .D1T1   A31:A30,*A15--[1]
64 || MVKL    1,A4
65
66    STDW    .D2T2   B29:B28,*SP--[1]
67 || STDW    .D1T1   A29:A28,*A15--[1]
68    STDW    .D2T2   B27:B26,*SP--[1]
69 || STDW    .D1T1   A27:A26,*A15--[1]
70    STDW    .D2T2   B25:B24,*SP--[1]
71 || STDW    .D1T1   A25:A24,*A15--[1]
72    STDW    .D2T2   B23:B22,*SP--[1]
73 || STDW    .D1T1   A23:A22,*A15--[1]
74    STDW    .D2T2   B21:B20,*SP--[1]
75 || STDW    .D1T1   A21:A20,*A15--[1]
76    STDW    .D2T2   B19:B18,*SP--[1]
77 || STDW    .D1T1   A19:A18,*A15--[1]
78    STDW    .D2T2   B17:B16,*SP--[1]
79 || STDW    .D1T1   A17:A16,*A15--[1]
80
81    STDW    .D2T2   B13:B12,*SP--[1]    ; save PC and CSR
82    STDW    .D2T2   B11:B10,*SP--[1]    ; save RILC and ILC
83    STDW    .D2T1   A5:A4,*SP--[1]      ; save TSR and  orig A4(stack type)
84            .endm
85
86RESTORE_ALL .macro  __rp, __tsr
87    LDDW    .D2T2   *++SP[1],B9:B8      ; get TSR (B9)
88    LDDW    .D2T2   *++SP[1],B11:B10    ; get RILC (B11) and ILC (B10)
89    LDDW    .D2T2   *++SP[1],B13:B12    ; get PC (B13) and CSR (B12)
90
91    ADDAW   .D1X    SP,30,A15
92
93    LDDW    .D1T1   *++A15[1],A17:A16
94 || LDDW    .D2T2   *++SP[1],B17:B16
95    LDDW    .D1T1   *++A15[1],A19:A18
96 || LDDW    .D2T2   *++SP[1],B19:B18
97    LDDW    .D1T1   *++A15[1],A21:A20
98 || LDDW    .D2T2   *++SP[1],B21:B20
99    LDDW    .D1T1   *++A15[1],A23:A22
100 || LDDW    .D2T2   *++SP[1],B23:B22
101    LDDW    .D1T1   *++A15[1],A25:A24
102 || LDDW    .D2T2   *++SP[1],B25:B24
103    LDDW    .D1T1   *++A15[1],A27:A26
104 || LDDW    .D2T2   *++SP[1],B27:B26
105    LDDW    .D1T1   *++A15[1],A29:A28
106 || LDDW    .D2T2   *++SP[1],B29:B28
107    LDDW    .D1T1   *++A15[1],A31:A30
108 || LDDW    .D2T2   *++SP[1],B31:B30
109
110    LDDW    .D1T1   *++A15[1],A1:A0
111 || LDDW    .D2T2   *++SP[1],B1:B0
112    LDDW    .D1T1   *++A15[1],A3:A2
113 || LDDW    .D2T2   *++SP[1],B3:B2
114 || MVC .S2 B9,__tsr
115    LDDW    .D1T1   *++A15[1],A5:A4
116 || LDDW    .D2T2   *++SP[1],B5:B4
117 || MVC .S2 B11,RILC
118    LDDW    .D1T1   *++A15[1],A7:A6
119 || LDDW    .D2T2   *++SP[1],B7:B6
120 || MVC .S2 B10,ILC
121    LDDW    .D1T1   *++A15[1],A9:A8
122 || LDDW    .D2T2   *++SP[1],B9:B8
123 || MVC .S2 B13,__rp
124
125    LDDW    .D1T1   *++A15[1],A11:A10
126 || LDDW    .D2T2   *++SP[1],B11:B10
127 || MVC .S2 B12,CSR
128    LDDW    .D1T1   *++A15[1],A13:A12
129 || LDDW    .D2T2   *++SP[1],B13:B12
130
131    MV  .D2X    A15,SP
132 || MVKL    .S1 rt_system_stack_top,A15
133    MVKH    .S1 rt_system_stack_top,A15
134 || ADDAW   .D1X    SP,6,A14
135    STW .D1T1   A14,*A15                ; save system stack pointer
136
137    LDDW    .D2T1   *++SP[1],A15:A14
138    LDDW    .D2T2   *+SP[1],SP:DP
139    NOP     4
140            .endm
141
142THREAD_SAVE_ALL .macro  __rp, __tsr
143    STDW    .D2T2   SP:DP,*--SP[1]
144    SUBAW   .D2 SP,2,SP
145
146    ADD .D1X    SP,-8,A15
147 || STDW    .D2T1   A15:A14,*SP--[16]   ; save A15:A14
148
149    STDW    .D2T2   B13:B12,*SP--[1]
150 || STDW    .D1T1   A13:A12,*A15--[1]
151 || MVC .S2 __rp,B13
152    STDW    .D2T2   B11:B10,*SP--[1]
153 || STDW    .D1T1   A11:A10,*A15--[1]
154 || MVC .S2 CSR,B12
155
156    STDW    .D2T2   B9:B8,*SP--[1]
157 || STDW    .D1T1   A9:A8,*A15--[1]
158 || MVC .S2 RILC,B11
159    STDW    .D2T2   B7:B6,*SP--[1]
160 || STDW    .D1T1   A7:A6,*A15--[1]
161 || MVC .S2 ILC,B10
162    STDW    .D2T2   B5:B4,*SP--[1]
163 || STDW    .D1T1   A5:A4,*A15--[1]
164    STDW    .D2T2   B3:B2,*SP--[1]
165 || STDW    .D1T1   A3:A2,*A15--[1]
166 || MVC .S2 __tsr,B5
167    STDW    .D2T2   B1:B0,*SP--[1]
168 || STDW    .D1T1   A1:A0,*A15--[1]
169 || MV  .S1X    B5,A5
170
171    STDW    .D2T2   B31:B30,*SP--[1]
172 || STDW    .D1T1   A31:A30,*A15--[1]
173 || MVKL    1,A4
174    STDW    .D2T2   B29:B28,*SP--[1]
175 || STDW    .D1T1   A29:A28,*A15--[1]
176    STDW    .D2T2   B27:B26,*SP--[1]
177 || STDW    .D1T1   A27:A26,*A15--[1]
178    STDW    .D2T2   B25:B24,*SP--[1]
179 || STDW    .D1T1   A25:A24,*A15--[1]
180    STDW    .D2T2   B23:B22,*SP--[1]
181 || STDW    .D1T1   A23:A22,*A15--[1]
182    STDW    .D2T2   B21:B20,*SP--[1]
183 || STDW    .D1T1   A21:A20,*A15--[1]
184    STDW    .D2T2   B19:B18,*SP--[1]
185 || STDW    .D1T1   A19:A18,*A15--[1]
186    STDW    .D2T2   B17:B16,*SP--[1]
187 || STDW    .D1T1   A17:A16,*A15--[1]
188
189    STDW    .D2T2   B13:B12,*SP--[1]    ; save PC and CSR
190    STDW    .D2T2   B11:B10,*SP--[1]    ; save RILC and ILC
191    STDW    .D2T1   A5:A4,*SP--[1]      ; save TSR and orig A4(stack type)
192                .endm
193