1;
2; Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
3;
4; SPDX-License-Identifier: Apache-2.0
5;
6; Change Logs:
7; Date           Author       Notes
8; 2021-11-16     Dystopia     the first version
9;
10
11;-----------------------------------------------------------
12;      interrupt and execption handler for C6000 DSP
13;-----------------------------------------------------------
14
15;-----------------------------------------------------------
16;                    macro definition
17;-----------------------------------------------------------
18DP  .set    B14
19SP  .set    B15
20;
21;-----------------------------------------------------------
22;
23    .include "contextinc.asm"
24;-----------------------------------------------------------
25;                     global function
26;-----------------------------------------------------------
27    .global _nmi_handler
28    .global _bad_handler
29    .global _int4_handler
30    .global _int5_handler
31    .global _int6_handler
32    .global _int7_handler
33    .global _int8_handler
34    .global _int9_handler
35    .global _int10_handler
36    .global _int11_handler
37    .global _int12_handler
38    .global _int13_handler
39    .global _int14_handler
40    .global _int15_handler
41;
42;-----------------------------------------------------------
43;
44
45;-----------------------------------------------------------
46;                     extern function
47;-----------------------------------------------------------
48    .ref hw_nmi_handler
49    .ref hw_bad_handler
50    .ref hw_int4_handler
51    .ref hw_int5_handler
52    .ref hw_int6_handler
53    .ref hw_int7_handler
54    .ref hw_int8_handler
55    .ref hw_int9_handler
56    .ref hw_int10_handler
57    .ref hw_int11_handler
58    .ref hw_int12_handler
59    .ref hw_int13_handler
60    .ref hw_int14_handler
61    .ref hw_int15_handler
62    .ref rt_hw_process_exception
63    .ref rt_interrupt_context_restore
64;
65;-----------------------------------------------------------
66;
67
68;-----------------------------------------------------------
69;               interrupt macro definition
70;-----------------------------------------------------------
71RT_INTERRUPT_ENTRY  .macro
72    SAVE_ALL    IRP,ITSR
73                    .endm
74
75RT_CALL_INT .macro __isr
76    B   __isr
77    ADDKPC  $1  ,B3,4
78$1:
79    B   .S1 rt_interrupt_context_restore
80    NOP 5
81            .endm
82;-----------------------------------------------------------
83;               execption macro definition
84;-----------------------------------------------------------
85RT_EXECPTION_ENTRY  .macro
86    SAVE_ALL NRP,NTSR
87                    .endm
88
89RT_EXECPTION_EXIT   .macro
90    RESTORE_ALL NRP,NTSR
91    B   .S2 NRP   ; return from execption
92    NOP 5
93                    .endm
94
95;
96;-----------------------------------------------------------
97;
98
99    .sect   ".text"
100;
101;-----------------------------------------------------------
102;
103
104;-----------------------------------------------------------
105; handler NMI interrupt
106;-----------------------------------------------------------
107_nmi_handler:
108;{
109    RT_EXECPTION_ENTRY
110    MVC .S2 EFR,B2
111    CMPEQ   .L2 1,B2,B2
112 || MVC .S2 TSR,B1
113    MV  .D1X    B2,A2
114 || CLR .S2 B1,10,10,B1
115    MVC .S2 B1,TSR
116 [!A2]  MVKL    .S1 rt_hw_process_exception,A0
117 ||[B2] MVKL    .S2 rt_hw_software_exception,B1
118 [!A2]  MVKH    .S1 rt_hw_process_exception,A0
119 ||[B2] MVKH    .S2 rt_hw_software_exception,B1
120 [!B2]  B   .S2X    A0
121 [B2]   B   .S2 B1
122 [!B2]  ADDAW   .D2 SP,2,B1
123 [!B2]  MV  .D1X    B1,A4
124    ADDKPC  .S2 ret_from_trap,B3,2
125;
126; return from trap
127;
128ret_from_trap:
129    MV  .D2X    A4,B0
130 [!B0]  MVKL    .S2 ret_from_exception,B3
131 [!B0]  MVKH    .S2 ret_from_exception,B3
132 [!B0]  BNOP    .S2 B3,5
133;
134; return from trap restore exception context
135;
136ret_from_exception:
137    RT_EXECPTION_EXIT
138;
139rt_hw_software_exception:
140    MVKL    .S1 rt_hw_process_exception,A0
141    MVKH    .S1 rt_hw_process_exception,A0
142    B   .S2X    A0
143    ADDAW   .D2 SP,2,B1
144    MV  .D1X    B1,A4
145    ADDKPC  .S2 ret_from_trap,B3,2
146    NOP 2
147;}
148
149;-----------------------------------------------------------
150; handler bad interrupt
151;-----------------------------------------------------------
152_bad_handler:
153;{
154    RT_INTERRUPT_ENTRY
155    RT_CALL_INT hw_bad_handler
156;}
157
158;-----------------------------------------------------------
159; handler INT4 interrupt
160;-----------------------------------------------------------
161_int4_handler:
162;{
163    RT_INTERRUPT_ENTRY
164    RT_CALL_INT hw_int4_handler
165;}
166
167;-----------------------------------------------------------
168; handler INT5 interrupt
169;-----------------------------------------------------------
170_int5_handler:
171;{
172    RT_INTERRUPT_ENTRY
173    RT_CALL_INT hw_int5_handler
174;}
175
176;-----------------------------------------------------------
177; handler INT6 interrupt
178;-----------------------------------------------------------
179_int6_handler:
180;{
181    RT_INTERRUPT_ENTRY
182    RT_CALL_INT hw_int6_handler
183;}
184
185;-----------------------------------------------------------
186; handler INT7 interrupt
187;-----------------------------------------------------------
188_int7_handler:
189;{
190    RT_INTERRUPT_ENTRY
191    RT_CALL_INT hw_int7_handler
192;}
193;-----------------------------------------------------------
194; handler INT8 interrupt
195;-----------------------------------------------------------
196_int8_handler:
197;{
198    RT_INTERRUPT_ENTRY
199    RT_CALL_INT hw_int8_handler
200;}
201
202;-----------------------------------------------------------
203; handler INT9 interrupt
204;-----------------------------------------------------------
205_int9_handler:
206;{
207    RT_INTERRUPT_ENTRY
208    RT_CALL_INT hw_int9_handler
209;}
210
211;-----------------------------------------------------------
212; handler INT10 interrupt
213;-----------------------------------------------------------
214_int10_handler:
215;{
216    RT_INTERRUPT_ENTRY
217    RT_CALL_INT hw_int10_handler
218;}
219
220;-----------------------------------------------------------
221; handler INT11 interrupt
222;-----------------------------------------------------------
223_int11_handler:
224;{
225    RT_INTERRUPT_ENTRY
226    RT_CALL_INT hw_int11_handler
227;}
228
229;-----------------------------------------------------------
230; handler INT12 interrupt
231;-----------------------------------------------------------
232_int12_handler:
233;{
234    RT_INTERRUPT_ENTRY
235    RT_CALL_INT hw_int12_handler
236;}
237
238;-----------------------------------------------------------
239; handler INT13 interrupt
240;-----------------------------------------------------------
241_int13_handler:
242;{
243    RT_INTERRUPT_ENTRY
244    RT_CALL_INT hw_int13_handler
245;}
246
247;-----------------------------------------------------------
248; handler INT14 interrupt
249;-----------------------------------------------------------
250_int14_handler:
251;{
252    RT_INTERRUPT_ENTRY
253    RT_CALL_INT hw_int14_handler
254;}
255;-----------------------------------------------------------
256; handler INT15 interrupt
257;-----------------------------------------------------------
258_int15_handler:
259;{
260    RT_INTERRUPT_ENTRY
261    RT_CALL_INT hw_int15_handler
262;}
263    .end
264