1 /* 2 * Copyright (c) 2018 ARM Limited 3 * 4 * Licensed under the Apache License, Version 2.0 (the "License"); 5 * you may not use this file except in compliance with the License. 6 * You may obtain a copy of the License at 7 * 8 * http://www.apache.org/licenses/LICENSE-2.0 9 * 10 * Unless required by applicable law or agreed to in writing, software 11 * distributed under the License is distributed on an "AS IS" BASIS, 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 13 * See the License for the specific language governing permissions and 14 * limitations under the License. 15 */ 16 17 #ifndef __TARGET_CFG_H__ 18 #define __TARGET_CFG_H__ 19 20 #include "uart_stdout.h" 21 #include "tfm_peripherals_def.h" 22 23 #ifdef TFM_FIH_PROFILE_ON 24 #include "fih.h" 25 #endif 26 #define TFM_DRIVER_STDIO Driver_USART0 27 #define NS_DRIVER_STDIO Driver_USART0 28 /* 29 // <o>Floating Point Unit usage 30 // <0=> Secure state only 31 // <3=> Secure and Non-Secure state 32 // <i> Value for SCB->NSACR register bits CP10, CP11 33 */ 34 #define SCB_NSACR_CP10_11_VAL 3 35 36 /* 37 // <o>Treat floating-point registers as Secure 38 // <0=> Disabled 39 // <1=> Enabled 40 // <i> Value for FPU->FPCCR register bit TS 41 */ 42 #define FPU_FPCCR_TS_VAL 0 43 44 /* 45 // <o>Clear on return (CLRONRET) accessibility 46 // <0=> Secure and Non-Secure state 47 // <1=> Secure state only 48 // <i> Value for FPU->FPCCR register bit CLRONRETS 49 */ 50 #define FPU_FPCCR_CLRONRETS_VAL 0 51 52 /* 53 // <o>Clear floating-point caller saved registers on exception return 54 // <0=> Disabled 55 // <1=> Enabled 56 // <i> Value for FPU->FPCCR register bit CLRONRET 57 */ 58 #define FPU_FPCCR_CLRONRET_VAL 1 59 60 typedef enum 61 { 62 TFM_FALSE = 0U, 63 TFM_TRUE = !TFM_FALSE 64 } TFM_BoolTypeDef; 65 66 typedef enum 67 { 68 TFM_DISABLE = 0U, 69 TFM_ENABLE = !TFM_DISABLE 70 } TFM_FunctionalState; 71 72 struct sau_cfg_t { 73 uint32_t RNR; 74 uint32_t RBAR; 75 uint32_t RLAR; 76 TFM_BoolTypeDef nsc; 77 #ifdef FLOW_CONTROL 78 uint32_t flow_step_enable; 79 uint32_t flow_ctrl_enable; 80 uint32_t flow_step_check; 81 uint32_t flow_ctrl_check; 82 #endif 83 }; 84 85 /** 86 * \brief Store the addresses of memory regions 87 */ 88 struct memory_region_limits 89 { 90 uint32_t non_secure_code_start; 91 uint32_t non_secure_partition_base; 92 uint32_t non_secure_partition_limit; 93 uint32_t veneer_base; 94 uint32_t veneer_limit; 95 }; 96 97 /** 98 * \brief Holds the data necessary to do isolation for a specific peripheral. 99 */ 100 struct platform_data_t 101 { 102 uint32_t periph_start; 103 uint32_t periph_limit; 104 int16_t periph_ppc_bank; 105 int16_t periph_ppc_loc; 106 }; 107 108 /** 109 * \brief Configures the Memory Protection Controller. 110 */ 111 #ifdef TFM_FIH_PROFILE_ON 112 fih_int gtzc_init_cfg(void); 113 #else 114 void gtzc_init_cfg(void); 115 #endif 116 117 /** 118 * \brief pin mux configuration for non secure access 119 * */ 120 #ifdef TFM_FIH_PROFILE_ON 121 fih_int pinmux_init_cfg(void); 122 #else 123 void pinmux_init_cfg(void); 124 #endif 125 126 /** 127 * \brief Configures SAU and IDAU. 128 */ 129 #ifdef TFM_FIH_PROFILE_ON 130 fih_int sau_and_idau_cfg(void); 131 #else 132 void sau_and_idau_cfg(void); 133 #endif 134 135 /** 136 * \brief Enable Fault handling. 137 */ 138 enum tfm_plat_err_t enable_fault_handlers(void); 139 140 /** 141 * \brief Set NVIC interrupt target state to NS. 142 */ 143 enum tfm_plat_err_t nvic_interrupt_target_state_cfg(void); 144 145 146 /* Exported macro ------------------------------------------------------------*/ 147 /* Exported functions ------------------------------------------------------- */ 148 void Error_Handler(void); 149 #ifndef TFM_ERROR_HANDLER_NON_SECURE 150 void Error_Handler_rdp(void); 151 #else 152 #define Error_Handler_rdp Error_Handler 153 #endif 154 155 #endif /* __TARGET_CFG_H__ */ 156