1 /* 2 * Copyright (c) 2018-2021, Arm Limited. All rights reserved. 3 * Copyright (c) 2024 Cypress Semiconductor Corporation (an Infineon 4 * company) or an affiliate of Cypress Semiconductor Corporation. All rights 5 * reserved. 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 * 9 */ 10 #include <inttypes.h> 11 #include "config_spm.h" 12 #include "fih.h" 13 #include "utilities.h" 14 #include "tfm_hal_platform.h" 15 16 #ifdef CONFIG_TFM_BACKTRACE_ON_CORE_PANIC 17 #include "tfm_log.h" 18 #include "backtrace.h" 19 #endif 20 tfm_core_panic(void)21void tfm_core_panic(void) 22 { 23 (void)fih_delay(); 24 25 #ifdef CONFIG_TFM_BACKTRACE_ON_CORE_PANIC 26 tfm_dump_backtrace(__func__, tfm_log); 27 #endif 28 29 /* Suppress Pe111 (statement is unreachable) for IAR as redundant code is needed for FIH */ 30 #if defined(__ICCARM__) 31 #pragma diag_suppress = Pe111 32 #endif 33 #ifdef CONFIG_TFM_HALT_ON_CORE_PANIC 34 35 /* 36 * Halt instead of reboot to retain the backtrace that triggered 37 * the fault and thereby make it easier to debug. 38 */ 39 tfm_hal_system_halt(); 40 41 #ifdef TFM_FIH_PROFILE_ON 42 (void)fih_delay(); 43 44 tfm_hal_system_halt(); 45 #endif 46 47 #else /* CONFIG_TFM_HALT_ON_CORE_PANIC */ 48 /* 49 * FixMe: In the first stage, the SPM will restart the entire system when a 50 * programmer error is detected in either the SPE or NSPE. 51 * In the next stage, the specified error codes are also sent to any NSPE 52 * management firmware. The NSPE management firmware can then decide to pass 53 * those error codes back to the calling task or to use its own 54 * functionality for terminating an execution context. 55 */ 56 tfm_hal_system_reset(); 57 58 #ifdef TFM_FIH_PROFILE_ON 59 (void)fih_delay(); 60 61 tfm_hal_system_reset(); 62 #endif 63 64 #endif /* CONFIG_TFM_HALT_ON_CORE_PANIC */ 65 #if defined(__ICCARM__) 66 #pragma diag_default = Pe111 67 #endif 68 } 69