Lines Matching refs:read_aux_reg
192 mmu4.word = read_aux_reg(ARC_AUX_MMU_BCR); in pae_exists()
205 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); in icache_exists()
214 return !(read_aux_reg(ARC_AUX_IC_CTRL) & IC_CTRL_CACHE_DISABLE); in icache_enabled()
221 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); in dcache_exists()
230 return !(read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_CACHE_DISABLE); in dcache_enabled()
238 sbcr.word = read_aux_reg(ARC_BCR_SLC); in slc_exists()
262 sbcr.word = read_aux_reg(ARC_BCR_SLC); in slc_disable_supported()
276 return !(read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_DIS); in __slc_enabled()
283 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); in __slc_enable()
292 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); in __slc_disable()
356 cbcr.word = read_aux_reg(ARC_BCR_CLUSTER); in ioc_exists()
382 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); in __slc_entire_op()
397 read_aux_reg(ARC_AUX_SLC_CTRL); in __slc_entire_op()
400 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); in __slc_entire_op()
437 ctrl = read_aux_reg(ARC_AUX_SLC_CTRL); in __slc_rgn_op()
468 read_aux_reg(ARC_AUX_SLC_CTRL); in __slc_rgn_op()
470 while (read_aux_reg(ARC_AUX_SLC_CTRL) & SLC_CTRL_BUSY); in __slc_rgn_op()
521 slc_cfg.word = read_aux_reg(ARC_AUX_SLC_CONFIG); in read_decode_cache_bcr_arcv2()
547 ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD); in read_decode_cache_bcr()
554 dbcr.word = read_aux_reg(ARC_BCR_DC_BUILD); in read_decode_cache_bcr()
584 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) & in icache_enable()
595 write_aux_reg(ARC_AUX_IC_CTRL, read_aux_reg(ARC_AUX_IC_CTRL) | in icache_disable()
614 read_aux_reg(ARC_AUX_IC_CTRL); /* blocks */ in __ic_entire_invalidate()
639 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) & in dcache_enable()
659 write_aux_reg(ARC_AUX_DC_CTRL, read_aux_reg(ARC_AUX_DC_CTRL) | in dcache_disable()
691 ctrl = read_aux_reg(ARC_AUX_DC_CTRL); in __before_dc_op()
705 while (read_aux_reg(ARC_AUX_DC_CTRL) & DC_CTRL_FLUSH_STATUS); in __after_dc_op()