Lines Matching refs:decode_pll
162 static uint32_t decode_pll(struct mxc_pll_reg *pll, uint32_t infreq) in decode_pll() function
243 ret_val = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in get_lp_apm()
259 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_mcu_main_clk()
272 return decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_periph_clk()
276 return decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_periph_clk()
278 return decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_periph_clk()
330 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
333 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
336 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in get_standard_pll_sel_clk()
458 ret_val = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in get_ddr_clk()
953 freq = decode_pll(mxc_plls[PLL1_CLOCK], MXC_HCLK); in do_mx5_showclocks()
955 freq = decode_pll(mxc_plls[PLL2_CLOCK], MXC_HCLK); in do_mx5_showclocks()
957 freq = decode_pll(mxc_plls[PLL3_CLOCK], MXC_HCLK); in do_mx5_showclocks()
960 freq = decode_pll(mxc_plls[PLL4_CLOCK], MXC_HCLK); in do_mx5_showclocks()