Lines Matching refs:interface
122 pkind = cvmx_cfg_port[xi.node][xi.interface][index].ccpp_pknd; in __cvmx_helper_cfg_pknd()
143 return cvmx_cfg_port[xi.node][xi.interface][index].ccpp_bpid; in __cvmx_helper_cfg_bpid()
153 return cvmx_cfg_port[xi.node][xi.interface][index].ccpp_pko_port_base; in __cvmx_helper_cfg_pko_port_base()
163 return cvmx_cfg_port[xi.node][xi.interface][index].ccpp_pko_num_ports; in __cvmx_helper_cfg_pko_port_num()
486 int interface; in cvmx_helper_cfg_dft_nqueues() local
490 interface = __cvmx_helper_cfg_pko_port_interface(pko_port); in cvmx_helper_cfg_dft_nqueues()
491 mode = cvmx_helper_interface_get_mode(interface); in cvmx_helper_cfg_dft_nqueues()
501 else if ((interface >= 0) && (interface < n)) { in cvmx_helper_cfg_dft_nqueues()
502 ret = __cvmx_pko_queue_static_config[0].pknd.pko_cfg_iface[interface].queues_per_port; in cvmx_helper_cfg_dft_nqueues()
573 return cvmx_cfg_port[xi.node][xi.interface][index].valid; in cvmx_helper_is_port_valid()
582 cvmx_cfg_port[xi.node][xi.interface][index].valid = valid; in cvmx_helper_set_port_valid()
591 cvmx_cfg_port[xi.node][xi.interface][index].sgmii_phy_mode = valid; in cvmx_helper_set_mac_phy_mode()
600 return cvmx_cfg_port[xi.node][xi.interface][index].sgmii_phy_mode; in cvmx_helper_get_mac_phy_mode()
609 cvmx_cfg_port[xi.node][xi.interface][index].sgmii_1000x_mode = valid; in cvmx_helper_set_1000x_mode()
618 return cvmx_cfg_port[xi.node][xi.interface][index].sgmii_1000x_mode; in cvmx_helper_get_1000x_mode()
627 cvmx_cfg_port[xi.node][xi.interface][index].agl_rx_clk_delay_bypass = valid; in cvmx_helper_set_agl_rx_clock_delay_bypass()
636 return cvmx_cfg_port[xi.node][xi.interface][index].agl_rx_clk_delay_bypass; in cvmx_helper_get_agl_rx_clock_delay_bypass()
645 cvmx_cfg_port[xi.node][xi.interface][index].agl_rx_clk_skew = value; in cvmx_helper_set_agl_rx_clock_skew()
654 return cvmx_cfg_port[xi.node][xi.interface][index].agl_rx_clk_skew; in cvmx_helper_get_agl_rx_clock_skew()
663 cvmx_cfg_port[xi.node][xi.interface][index].agl_refclk_sel = value; in cvmx_helper_set_agl_refclk_sel()
672 return cvmx_cfg_port[xi.node][xi.interface][index].agl_refclk_sel; in cvmx_helper_get_agl_refclk_sel()
681 cvmx_cfg_port[xi.node][xi.interface][index].force_link_up = value; in cvmx_helper_set_port_force_link_up()
690 return cvmx_cfg_port[xi.node][xi.interface][index].force_link_up; in cvmx_helper_get_port_force_link_up()
699 cvmx_cfg_port[xi.node][xi.interface][index].phy_present = value; in cvmx_helper_set_port_phy_present()
708 return cvmx_cfg_port[xi.node][xi.interface][index].phy_present; in cvmx_helper_get_port_phy_present()
783 int cvmx_pko_alloc_iport_and_queues(int interface, int port, int port_cnt, int queue_cnt) in cvmx_pko_alloc_iport_and_queues() argument
787 debug("%s: intf %d/%d pcnt %d qcnt %d\n", __func__, interface, port, port_cnt, in cvmx_pko_alloc_iport_and_queues()
793 rv = cvmx_pko_internal_ports_alloc(interface, port, port_cnt); in cvmx_pko_alloc_iport_and_queues()
796 __func__, interface, port, port_cnt); in cvmx_pko_alloc_iport_and_queues()
799 port_start = __cvmx_helper_cfg_pko_port_base(interface, port); in cvmx_pko_alloc_iport_and_queues()
800 cnt = __cvmx_helper_cfg_pko_port_num(interface, port); in cvmx_pko_alloc_iport_and_queues()
802 port_start = cvmx_helper_get_ipd_port(interface, port); in cvmx_pko_alloc_iport_and_queues()
894 int num_interfaces, interface; in __cvmx_helper_init_port_config_data() local
971 for (interface = 0; interface < num_interfaces; interface++) { in __cvmx_helper_init_port_config_data()
972 int num_ports = __cvmx_helper_early_ports_on_interface(interface); in __cvmx_helper_init_port_config_data()
979 port_base = __cvmx_helper_cfg_pko_port_base(interface, port); in __cvmx_helper_init_port_config_data()
983 port_base = cvmx_helper_get_ipd_port(interface, port); in __cvmx_helper_init_port_config_data()
990 rv = cvmx_pko_alloc_iport_and_queues(interface, port, 1, 1); in __cvmx_helper_init_port_config_data()
1026 cvmx_cfg_port[xi.node][xi.interface][index].port_fdt_node = node_offset; in cvmx_helper_set_port_fdt_node_offset()
1043 return cvmx_cfg_port[xi.node][xi.interface][index].port_fdt_node; in cvmx_helper_get_port_fdt_node_offset()
1060 cvmx_cfg_port[xi.node][xi.interface][index].phy_fdt_node = node_offset; in cvmx_helper_set_phy_fdt_node_offset()
1077 return cvmx_cfg_port[xi.node][xi.interface][index].phy_fdt_node; in cvmx_helper_get_phy_fdt_node_offset()
1095 cvmx_cfg_port[xi.node][xi.interface][index].disable_an = !enable; in cvmx_helper_set_port_autonegotiation()
1113 return !cvmx_cfg_port[xi.node][xi.interface][index].disable_an; in cvmx_helper_get_port_autonegotiation()
1131 return cvmx_cfg_port[xi.node][xi.interface][index].enable_fec; in cvmx_helper_get_port_fec()
1148 cvmx_cfg_port[xi.node][xi.interface][index].phy_info = phy_info; in cvmx_helper_set_port_phy_info()
1166 return cvmx_cfg_port[xi.node][xi.interface][index].phy_info; in cvmx_helper_get_port_phy_info()
1185 return cvmx_cfg_port[xi.node][xi.interface][index].gpio_leds; in cvmx_helper_get_port_phy_leds()
1205 cvmx_cfg_port[xi.node][xi.interface][index].tx_clk_delay_bypass = bypass; in cvmx_helper_cfg_set_rgmii_tx_clk_delay()
1206 cvmx_cfg_port[xi.node][xi.interface][index].rgmii_tx_clk_delay = clk_delay; in cvmx_helper_cfg_set_rgmii_tx_clk_delay()
1226 *bypass = cvmx_cfg_port[xi.node][xi.interface][index].tx_clk_delay_bypass; in cvmx_helper_cfg_get_rgmii_tx_clk_delay()
1228 *clk_delay = cvmx_cfg_port[xi.node][xi.interface][index].rgmii_tx_clk_delay; in cvmx_helper_cfg_get_rgmii_tx_clk_delay()
1245 cvmx_cfg_port[xi.node][xi.interface][index].vsc7224_chan = vsc7224_chan_info; in cvmx_helper_cfg_set_vsc7224_chan_info()
1262 return cvmx_cfg_port[xi.node][xi.interface][index].sfp_info; in cvmx_helper_cfg_get_sfp_info()
1278 cvmx_cfg_port[xi.node][xi.interface][index].sfp_info = sfp_info; in cvmx_helper_cfg_set_sfp_info()