Lines Matching refs:csr_rd_node
2086 lane_vma_fine_ctrl_2.u64 = csr_rd_node(node, CVMX_GSERX_LANE_VMA_FINE_CTRL_2(qlm)); in octeon_qlm_dfe_disable()
2098 loop_ctrl.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_LOOP_CTRL(l, qlm)); in octeon_qlm_dfe_disable()
2110 ctrl_1.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_VALBBD_CTRL_1(l, qlm)); in octeon_qlm_dfe_disable()
2128 ctrl_0.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_VALBBD_CTRL_0(l, qlm)); in octeon_qlm_dfe_disable()
2145 ctrl_2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_VALBBD_CTRL_2(l, qlm)); in octeon_qlm_dfe_disable()
2228 lmode.u64 = csr_rd_node(node, CVMX_GSERX_LANE_MODE(qlm)); in octeon_qlm_dfe_disable_ctle_agc()
2231 px_mode_1.u64 = csr_rd_node(node, CVMX_GSERX_LANE_PX_MODE_1(lmode.s.lmode, qlm)); in octeon_qlm_dfe_disable_ctle_agc()
2243 ctrl_0.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_VALBBD_CTRL_0(l, qlm)); in octeon_qlm_dfe_disable_ctle_agc()
2251 loop_ctrl.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_LOOP_CTRL(l, qlm)); in octeon_qlm_dfe_disable_ctle_agc()
2260 lanex_pwr_ctrl.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PWR_CTRL(l, qlm)); in octeon_qlm_dfe_disable_ctle_agc()
2265 rx_cfg_5.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_CFG_5(l, qlm)); in octeon_qlm_dfe_disable_ctle_agc()
2270 ctle_ctrl.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_CTLE_CTRL(l, qlm)); in octeon_qlm_dfe_disable_ctle_agc()
2274 rx_cfg_2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_CFG_2(l, qlm)); in octeon_qlm_dfe_disable_ctle_agc()
2309 gserx_cfg.u64 = csr_rd_node(node, CVMX_GSERX_CFG(qlm)); in octeon_qlm_tune_per_lane_v3()
2330 pmd_control.u64 = csr_rd_node(node, CVMX_BGXX_SPUX_BR_PMD_CONTROL(lmac, bgx)); in octeon_qlm_tune_per_lane_v3()
2390 tx_cfg1.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_TX_CFG_1(lane, qlm)); in octeon_qlm_tune_per_lane_v3()
2400 tx_cfg0.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_TX_CFG_0(lane, qlm)); in octeon_qlm_tune_per_lane_v3()
2406 pre_emphasis.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_TX_PRE_EMPHASIS(lane, qlm)); in octeon_qlm_tune_per_lane_v3()
2413 tx_cfg3.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_TX_CFG_3(lane, qlm)); in octeon_qlm_tune_per_lane_v3()
2420 tx_cfg3.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_TX_CFG_3(lane, qlm)); in octeon_qlm_tune_per_lane_v3()
2426 pcs_ctlifc_0.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_0(lane, qlm)); in octeon_qlm_tune_per_lane_v3()
2434 pcs_ctlifc_2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(lane, qlm)); in octeon_qlm_tune_per_lane_v3()
2442 pcs_ctlifc_2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(lane, qlm)); in octeon_qlm_tune_per_lane_v3()
2451 pcs_ctlifc_2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(lane, qlm)); in octeon_qlm_tune_per_lane_v3()
2455 pcs_ctlifc_2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(lane, qlm)); in octeon_qlm_tune_per_lane_v3()
2500 lane_vma_fine_ctrl_2.u64 = csr_rd_node(node, CVMX_GSERX_LANE_VMA_FINE_CTRL_2(qlm)); in octeon_qlm_set_channel_v3()
2529 ctlifc_2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(lane, qlm)); in __qlm_init_errata_20844()
2533 misc_ovrrd.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_MISC_OVRRD(lane, qlm)); in __qlm_init_errata_20844()
2540 misc_ovrrd.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_MISC_OVRRD(lane, qlm)); in __qlm_init_errata_20844()
2544 ctlifc_2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(lane, qlm)); in __qlm_init_errata_20844()
3314 rx_txdir_ctrl.u64 = csr_rd_node(node, CVMX_GSERX_RX_TXDIR_CTRL_1(qlm)); in __qlm_kr_inc_dec_gser26636()
3341 csr_rd_node(node, CVMX_GSERX_LANEX_RX_VALBBD_CTRL_0(lane, qlm)); in __qlm_rx_eq_temp_gser27140()
3349 lane_vma_fine_ctrl_2.u64 = csr_rd_node(node, CVMX_GSERX_LANE_VMA_FINE_CTRL_2(qlm)); in __qlm_rx_eq_temp_gser27140()
3357 rx_txdir_ctrl_0.u64 = csr_rd_node(node, CVMX_GSERX_RX_TXDIR_CTRL_0(qlm)); in __qlm_rx_eq_temp_gser27140()
3364 lane_vma_fine_ctrl_0.u64 = csr_rd_node(node, CVMX_GSERX_LANE_VMA_FINE_CTRL_0(qlm)); in __qlm_rx_eq_temp_gser27140()
3376 rx_txdir_ctrl_1.u64 = csr_rd_node(node, CVMX_GSERX_RX_TXDIR_CTRL_1(qlm)); in __qlm_rx_eq_temp_gser27140()
3382 eq_wait_time.u64 = csr_rd_node(node, CVMX_GSERX_EQ_WAIT_TIME(qlm)); in __qlm_rx_eq_temp_gser27140()
3387 rx_txdir_ctrl_2.u64 = csr_rd_node(node, CVMX_GSERX_RX_TXDIR_CTRL_2(qlm)); in __qlm_rx_eq_temp_gser27140()
3410 pll_cfg_3.u64 = csr_rd_node(node, CVMX_GSERX_GLBL_PLL_CFG_3(qlm)); in __qlm_errata_gser_26150()
3416 misc_config_1.u64 = csr_rd_node(node, CVMX_GSERX_GLBL_MISC_CONFIG_1(qlm)); in __qlm_errata_gser_26150()
3423 pll_cfg_3.u64 = csr_rd_node(node, CVMX_GSERX_GLBL_PLL_CFG_3(qlm)); in __qlm_errata_gser_26150()
3450 ctlifc0.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_0(i, qlm)); in __qlm_errata_gser_26150()
3457 ctlifc1.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_1(i, qlm)); in __qlm_errata_gser_26150()
3465 ctlifc2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(i, qlm)); in __qlm_errata_gser_26150()
3472 ctlifc2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(i, qlm)); in __qlm_errata_gser_26150()
3481 pll_cfg_3.u64 = csr_rd_node(node, CVMX_GSERX_GLBL_PLL_CFG_3(qlm)); in __qlm_errata_gser_26150()
3487 misc_config_1.u64 = csr_rd_node(node, CVMX_GSERX_GLBL_MISC_CONFIG_1(qlm)); in __qlm_errata_gser_26150()
3501 ctlifc0.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_0(i, qlm)); in __qlm_errata_gser_26150()
3507 ctlifc1.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_1(i, qlm)); in __qlm_errata_gser_26150()
3515 ctlifc2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(i, qlm)); in __qlm_errata_gser_26150()
3522 ctlifc2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(i, qlm)); in __qlm_errata_gser_26150()
3534 ctlifc2.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PCS_CTLIFC_2(i, qlm)); in __qlm_errata_gser_26150()
3580 mode_0.u64 = csr_rd_node(node, CVMX_GSERX_PLL_PX_MODE_0(lane_mode, qlm)); in __qlm_setup_pll_cn78xx()
3581 mode_1.u64 = csr_rd_node(node, CVMX_GSERX_PLL_PX_MODE_1(lane_mode, qlm)); in __qlm_setup_pll_cn78xx()
3734 window_ctl.u64 = csr_rd_node(node, CVMX_PEXP_SLI_WINDOW_CTL); in __set_sli_window_ctl_errata_31375()
3755 pemx_on.u64 = csr_rd_node(node, CVMX_PEMX_ON(pem)); in __cvmx_qlm_pcie_errata_ep_cn78xx()
3763 pemx_on.u64 = csr_rd_node(node, CVMX_PEMX_ON(pem)); in __cvmx_qlm_pcie_errata_ep_cn78xx()
3769 pemx_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(pem)); in __cvmx_qlm_pcie_errata_ep_cn78xx()
3789 pemx_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(pem)); in __cvmx_qlm_pcie_errata_ep_cn78xx()
3802 csr_rd_node(node, CVMX_GSERX_LANEX_RX_MISC_OVRRD(lane, pem)); in __cvmx_qlm_pcie_errata_ep_cn78xx()
3806 pwr_ctrl.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PWR_CTRL(lane, pem)); in __cvmx_qlm_pcie_errata_ep_cn78xx()
3817 csr_rd_node(node, CVMX_GSERX_LANEX_RX_MISC_OVRRD(lane, pem)); in __cvmx_qlm_pcie_errata_ep_cn78xx()
3821 pwr_ctrl.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PWR_CTRL(lane, pem)); in __cvmx_qlm_pcie_errata_ep_cn78xx()
3856 pem_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(0)); in __cvmx_qlm_pcie_errata_cn78xx()
3862 pem_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(0)); in __cvmx_qlm_pcie_errata_cn78xx()
3868 pem_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(2)); in __cvmx_qlm_pcie_errata_cn78xx()
3874 pem_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(2)); in __cvmx_qlm_pcie_errata_cn78xx()
3875 pem3_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(3)); in __cvmx_qlm_pcie_errata_cn78xx()
3895 pem_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(pem)); in __cvmx_qlm_pcie_errata_cn78xx()
3906 slice_cfg.u64 = csr_rd_node(node, CVMX_GSERX_SLICE_CFG(low_qlm)); in __cvmx_qlm_pcie_errata_cn78xx()
3916 phy_ctl.u64 = csr_rd_node(node, CVMX_GSERX_PHY_CTL(q)); in __cvmx_qlm_pcie_errata_cn78xx()
3923 phy_ctl.u64 = csr_rd_node(node, CVMX_GSERX_PHY_CTL(q)); in __cvmx_qlm_pcie_errata_cn78xx()
3933 slice_cfg.u64 = csr_rd_node(node, CVMX_GSERX_SLICE_CFG(q)); in __cvmx_qlm_pcie_errata_cn78xx()
3942 pwr_ctrl_p1.u64 = csr_rd_node(node, CVMX_GSERX_RX_PWR_CTRL_P1(q)); in __cvmx_qlm_pcie_errata_cn78xx()
3955 tx_cfg.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_TX_CFG_0(i, q)); in __cvmx_qlm_pcie_errata_cn78xx()
3958 pwr_ctrl.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_PWR_CTRL(i, q)); in __cvmx_qlm_pcie_errata_cn78xx()
4025 pem_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(pem)); in __cvmx_qlm_pcie_errata_cn78xx()
4048 soft_prst.u64 = csr_rd_node(node, CVMX_RST_SOFT_PRSTX(pem)); in __cvmx_qlm_pcie_errata_cn78xx()
4056 soft_prst.u64 = csr_rd_node(node, CVMX_RST_SOFT_PRSTX(pem)); in __cvmx_qlm_pcie_errata_cn78xx()
4077 rst_ctl.u64 = csr_rd_node(node, CVMX_RST_CTLX(pem)); in __setup_pem_reset()
4137 cfg.u64 = csr_rd_node(node, CVMX_GSERX_CFG(qlm)); in octeon_configure_qlm_cn78xx()
4162 phy_ctl.u64 = csr_rd_node(node, CVMX_GSERX_PHY_CTL(qlm)); in octeon_configure_qlm_cn78xx()
4180 refclk_sel.u64 = csr_rd_node(node, CVMX_GSERX_REFCLK_SEL(qlm)); in octeon_configure_qlm_cn78xx()
4190 refclk_sel.u64 = csr_rd_node(node, CVMX_GSERX_REFCLK_SEL(qlm)); in octeon_configure_qlm_cn78xx()
4209 rst_prst.u64 = csr_rd_node(node, CVMX_RST_SOFT_PRSTX(0)); in octeon_configure_qlm_cn78xx()
4214 pemx_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(0)); in octeon_configure_qlm_cn78xx()
4221 pemx_on.u64 = csr_rd_node(node, CVMX_PEMX_ON(0)); in octeon_configure_qlm_cn78xx()
4233 rst_prst.u64 = csr_rd_node(node, CVMX_RST_SOFT_PRSTX(1)); in octeon_configure_qlm_cn78xx()
4238 pemx_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(1)); in octeon_configure_qlm_cn78xx()
4244 pemx_on.u64 = csr_rd_node(node, CVMX_PEMX_ON(1)); in octeon_configure_qlm_cn78xx()
4248 pemx_on.u64 = csr_rd_node(node, CVMX_PEMX_ON(0)); in octeon_configure_qlm_cn78xx()
4258 rst_prst.u64 = csr_rd_node(node, CVMX_RST_SOFT_PRSTX(2)); in octeon_configure_qlm_cn78xx()
4263 pemx_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(2)); in octeon_configure_qlm_cn78xx()
4270 pemx_on.u64 = csr_rd_node(node, CVMX_PEMX_ON(2)); in octeon_configure_qlm_cn78xx()
4278 pemx_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(2)); in octeon_configure_qlm_cn78xx()
4282 pemx_on.u64 = csr_rd_node(node, CVMX_PEMX_ON(2)); in octeon_configure_qlm_cn78xx()
4290 rst_prst.u64 = csr_rd_node(node, CVMX_RST_SOFT_PRSTX(3)); in octeon_configure_qlm_cn78xx()
4295 pemx_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(3)); in octeon_configure_qlm_cn78xx()
4301 pemx_on.u64 = csr_rd_node(node, CVMX_PEMX_ON(3)); in octeon_configure_qlm_cn78xx()
4312 pemx_on.u64 = csr_rd_node(node, CVMX_PEMX_ON(3)); in octeon_configure_qlm_cn78xx()
4320 rst_prst.u64 = csr_rd_node(node, CVMX_RST_SOFT_PRSTX(3)); in octeon_configure_qlm_cn78xx()
4325 pemx_cfg.u64 = csr_rd_node(node, CVMX_PEMX_CFG(3)); in octeon_configure_qlm_cn78xx()
4331 pemx_qlm.u64 = csr_rd_node(node, CVMX_PEMX_QLM(3)); in octeon_configure_qlm_cn78xx()
4334 pemx_on.u64 = csr_rd_node(node, CVMX_PEMX_ON(3)); in octeon_configure_qlm_cn78xx()
4407 phy_ctl.u64 = csr_rd_node(node, CVMX_GSERX_PHY_CTL(qlm)); in octeon_configure_qlm_cn78xx()
4430 phy_ctl.u64 = csr_rd_node(node, CVMX_GSERX_PHY_CTL(qlm)); in octeon_configure_qlm_cn78xx()
4442 cfg.u64 = csr_rd_node(node, CVMX_GSERX_CFG(qlm)); in octeon_configure_qlm_cn78xx()
4451 lmode.u64 = csr_rd_node(node, CVMX_GSERX_LANE_MODE(qlm)); in octeon_configure_qlm_cn78xx()
4463 global_cfg.u64 = csr_rd_node(node, CVMX_BGXX_CMR_GLOBAL_CONFIG(bgx)); in octeon_configure_qlm_cn78xx()
4469 phy_ctl.u64 = csr_rd_node(node, CVMX_GSERX_PHY_CTL(qlm)); in octeon_configure_qlm_cn78xx()
4472 csr_rd_node(node, CVMX_GSERX_PHY_CTL(qlm)); in octeon_configure_qlm_cn78xx()
4486 cmr_config.u64 = csr_rd_node(node, CVMX_BGXX_CMRX_CONFIG(index, bgx)); in octeon_configure_qlm_cn78xx()
4505 csr_rd_node(node, CVMX_BGXX_SPUX_BR_PMD_CONTROL(index, bgx)); in octeon_configure_qlm_cn78xx()
4589 cfg4.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_RX_CFG_4(l, qlm)); in octeon_configure_qlm_cn78xx()
4593 cfg0.u64 = csr_rd_node(node, CVMX_GSERX_LANEX_TX_CFG_0(l, qlm)); in octeon_configure_qlm_cn78xx()
5830 phy_ctl.u64 = csr_rd_node(node, CVMX_GSERX_PHY_CTL(qlm)); in octeon_init_qlm()
5832 cfg.u64 = csr_rd_node(node, CVMX_GSERX_CFG(qlm)); in octeon_init_qlm()
5850 rst_ctl.u64 = csr_rd_node(node, CVMX_RST_CTLX(pem)); in octeon_init_qlm()