Lines Matching refs:ctrl_num
87 const unsigned int ctrl_num) in compute_cas_write_latency() argument
90 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in compute_cas_write_latency()
121 const unsigned int ctrl_num) in compute_cas_write_latency() argument
124 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in compute_cas_write_latency()
297 static void set_timing_cfg_0(const unsigned int ctrl_num, in set_timing_cfg_0() argument
317 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in set_timing_cfg_0()
323 unsigned int data_rate = get_ddr_freq(ctrl_num); in set_timing_cfg_0()
345 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); in set_timing_cfg_0()
351 tmrd_mclk = max(24U, picos_to_mclk(ctrl_num, 15000)); in set_timing_cfg_0()
353 unsigned int data_rate = get_ddr_freq(ctrl_num); in set_timing_cfg_0()
368 ip_rev = fsl_ddr_get_version(ctrl_num); in set_timing_cfg_0()
376 picos_to_mclk(ctrl_num, 15000)); in set_timing_cfg_0()
420 act_pd_exit_mclk = picos_to_mclk(ctrl_num, txp); in set_timing_cfg_0()
456 static void set_timing_cfg_3(const unsigned int ctrl_num, in set_timing_cfg_3() argument
480 ext_pretoact = picos_to_mclk(ctrl_num, common_dimm->trp_ps) >> 4; in set_timing_cfg_3()
481 ext_acttopre = picos_to_mclk(ctrl_num, common_dimm->tras_ps) >> 4; in set_timing_cfg_3()
482 ext_acttorw = picos_to_mclk(ctrl_num, common_dimm->trcd_ps) >> 4; in set_timing_cfg_3()
486 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8) >> 4; in set_timing_cfg_3()
488 ext_refrec = (picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8) >> 4; in set_timing_cfg_3()
491 ext_wrrec = (picos_to_mclk(ctrl_num, common_dimm->twr_ps) + in set_timing_cfg_3()
508 static void set_timing_cfg_1(const unsigned int ctrl_num, in set_timing_cfg_1() argument
544 pretoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trp_ps); in set_timing_cfg_1()
545 acttopre_mclk = picos_to_mclk(ctrl_num, common_dimm->tras_ps); in set_timing_cfg_1()
546 acttorw_mclk = picos_to_mclk(ctrl_num, common_dimm->trcd_ps); in set_timing_cfg_1()
574 if (fsl_ddr_get_version(ctrl_num) <= 0x40400) in set_timing_cfg_1()
581 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc1_ps) - 8; in set_timing_cfg_1()
582 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_timing_cfg_1()
583 acttoact_mclk = max(picos_to_mclk(ctrl_num, common_dimm->trrds_ps), 4U); in set_timing_cfg_1()
584 wrtord_mclk = max(2U, picos_to_mclk(ctrl_num, 2500)); in set_timing_cfg_1()
590 refrec_ctrl = picos_to_mclk(ctrl_num, common_dimm->trfc_ps) - 8; in set_timing_cfg_1()
591 wrrec_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_timing_cfg_1()
592 acttoact_mclk = picos_to_mclk(ctrl_num, common_dimm->trrd_ps); in set_timing_cfg_1()
593 wrtord_mclk = picos_to_mclk(ctrl_num, common_dimm->twtr_ps); in set_timing_cfg_1()
636 static void set_timing_cfg_2(const unsigned int ctrl_num, in set_timing_cfg_2() argument
658 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in set_timing_cfg_2()
676 wr_lat = compute_cas_write_latency(ctrl_num); in set_timing_cfg_2()
680 rd_to_pre = picos_to_mclk(ctrl_num, 7500); in set_timing_cfg_2()
682 rd_to_pre = picos_to_mclk(ctrl_num, common_dimm->trtp_ps); in set_timing_cfg_2()
700 cke_pls = max(3U, picos_to_mclk(ctrl_num, 5000)); in set_timing_cfg_2()
707 cke_pls = max(3U, picos_to_mclk(ctrl_num, mclk_ps > 1870 ? 7500 : in set_timing_cfg_2()
712 four_act = picos_to_mclk(ctrl_num, in set_timing_cfg_2()
729 static void set_ddr_sdram_rcw(const unsigned int ctrl_num, in set_ddr_sdram_rcw() argument
734 unsigned int ddr_freq = get_ddr_freq(ctrl_num) / 1000000; in set_ddr_sdram_rcw()
875 static void set_ddr_sdram_cfg_2(const unsigned int ctrl_num, in set_ddr_sdram_cfg_2() argument
923 slow = get_ddr_freq(ctrl_num) < 1249000000; in set_ddr_sdram_cfg_2()
977 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, in set_ddr_sdram_mode_2() argument
989 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 9; in set_ddr_sdram_mode_2()
992 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in set_ddr_sdram_mode_2()
1065 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, in set_ddr_sdram_mode_2() argument
1077 unsigned int cwl = compute_cas_write_latency(ctrl_num) - 5; in set_ddr_sdram_mode_2()
1141 static void set_ddr_sdram_mode_2(const unsigned int ctrl_num, in set_ddr_sdram_mode_2() argument
1272 static void set_ddr_sdram_mode_10(const unsigned int ctrl_num, in set_ddr_sdram_mode_10() argument
1281 unsigned int tccdl_min = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); in set_ddr_sdram_mode_10()
1328 static void set_ddr_sdram_interval(const unsigned int ctrl_num, in set_ddr_sdram_interval() argument
1336 refint = picos_to_mclk(ctrl_num, common_dimm->refresh_rate_ps); in set_ddr_sdram_interval()
1350 static void set_ddr_sdram_mode(const unsigned int ctrl_num, in set_ddr_sdram_mode() argument
1426 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_ddr_sdram_mode()
1521 static void set_ddr_sdram_mode(const unsigned int ctrl_num, in set_ddr_sdram_mode() argument
1601 wr_mclk = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_ddr_sdram_mode()
1717 static void set_ddr_sdram_mode(const unsigned int ctrl_num, in set_ddr_sdram_mode() argument
1790 wr = picos_to_mclk(ctrl_num, common_dimm->twr_ps); in set_ddr_sdram_mode()
1973 static void set_timing_cfg_7(const unsigned int ctrl_num, in set_timing_cfg_7() argument
1980 const unsigned int mclk_ps = get_memory_clk_period_ps(ctrl_num); in set_timing_cfg_7()
1982 txpr = max(5U, picos_to_mclk(ctrl_num, common_dimm->trfc1_ps + 10000)); in set_timing_cfg_7()
1983 tcksre = max(5U, picos_to_mclk(ctrl_num, 10000)); in set_timing_cfg_7()
1984 tcksrx = max(5U, picos_to_mclk(ctrl_num, 10000)); in set_timing_cfg_7()
2024 static void set_timing_cfg_8(const unsigned int ctrl_num, in set_timing_cfg_8() argument
2032 int tccdl = picos_to_mclk(ctrl_num, common_dimm->tccdl_ps); in set_timing_cfg_8()
2056 acttoact_bg = picos_to_mclk(ctrl_num, common_dimm->trrdl_ps); in set_timing_cfg_8()
2057 wrtord_bg = max(4U, picos_to_mclk(ctrl_num, 7500)); in set_timing_cfg_8()
2076 static void set_timing_cfg_9(const unsigned int ctrl_num, in set_timing_cfg_9() argument
2086 picos_to_mclk(ctrl_num, common_dimm->trfc_slr_ps); in set_timing_cfg_9()
2325 compute_fsl_memctl_config_regs(const unsigned int ctrl_num, in compute_fsl_memctl_config_regs() argument
2498 set_timing_cfg_0(ctrl_num, ddr, popts, dimm_params); in compute_fsl_memctl_config_regs()
2501 set_timing_cfg_3(ctrl_num, ddr, popts, common_dimm, cas_latency, in compute_fsl_memctl_config_regs()
2503 set_timing_cfg_1(ctrl_num, ddr, popts, common_dimm, cas_latency); in compute_fsl_memctl_config_regs()
2504 set_timing_cfg_2(ctrl_num, ddr, popts, common_dimm, in compute_fsl_memctl_config_regs()
2510 ip_rev = fsl_ddr_get_version(ctrl_num); in compute_fsl_memctl_config_regs()
2517 set_ddr_sdram_cfg_2(ctrl_num, ddr, popts, unq_mrs_en); in compute_fsl_memctl_config_regs()
2518 set_ddr_sdram_mode(ctrl_num, ddr, popts, common_dimm, in compute_fsl_memctl_config_regs()
2520 set_ddr_sdram_mode_2(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2523 set_ddr_sdram_mode_10(ctrl_num, ddr, popts, common_dimm, unq_mrs_en); in compute_fsl_memctl_config_regs()
2525 set_ddr_sdram_rcw(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2527 set_ddr_sdram_interval(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2537 set_timing_cfg_7(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()
2538 set_timing_cfg_8(ctrl_num, ddr, popts, common_dimm, cas_latency); in compute_fsl_memctl_config_regs()
2539 set_timing_cfg_9(ctrl_num, ddr, popts, common_dimm); in compute_fsl_memctl_config_regs()