Lines Matching refs:ctrl
65 static void ddr_set_arbiter(struct ddr2_ctrl_regs *ctrl, in ddr_set_arbiter() argument
72 writel(i * MIN_LIM_WIDTH, &ctrl->tsel); in ddr_set_arbiter()
73 writel(param->min_limit, &ctrl->minlim); in ddr_set_arbiter()
76 writel(i * RQST_PERIOD_WIDTH, &ctrl->tsel); in ddr_set_arbiter()
77 writel(param->req_period, &ctrl->reqprd); in ddr_set_arbiter()
80 writel(i * MIN_CMDACPT_WIDTH, &ctrl->tsel); in ddr_set_arbiter()
81 writel(param->min_cmd_acpt, &ctrl->mincmd); in ddr_set_arbiter()
99 static void host_load_cmd(struct ddr2_ctrl_regs *ctrl, u32 cmd_idx, in host_load_cmd() argument
105 writel(hostcmd1, &ctrl->cmd10[cmd_idx]); in host_load_cmd()
106 writel((hostcmd2 & 0x7ff) | (hc_delay << 11), &ctrl->cmd20[cmd_idx]); in host_load_cmd()
115 struct ddr2_ctrl_regs *ctrl; in ddr2_ctrl_init() local
117 ctrl = ioremap(PIC32_DDR2C_BASE, sizeof(*ctrl)); in ddr2_ctrl_init()
120 writel(HALF_RATE_MODE, &ctrl->memwidth); in ddr2_ctrl_init()
124 ddr_set_arbiter(ctrl, arb_params); in ddr2_ctrl_init()
129 (EN_AUTO_PRECH << 30)), &ctrl->memcfg0); in ddr2_ctrl_init()
131 writel(ROW_ADDR_MASK, &ctrl->memcfg1); in ddr2_ctrl_init()
132 writel(COL_HI_MASK, &ctrl->memcfg2); in ddr2_ctrl_init()
133 writel(COL_LO_MASK, &ctrl->memcfg3); in ddr2_ctrl_init()
134 writel(BA_MASK | (CS_ADDR_MASK << 8), &ctrl->memcfg4); in ddr2_ctrl_init()
140 &ctrl->refcfg); in ddr2_ctrl_init()
146 &ctrl->pwrcfg); in ddr2_ctrl_init()
167 ((RL - WL + 3) << 28)), &ctrl->dlycfg0); in ddr2_ctrl_init()
177 ((DIV_ROUND_UP(T_DLLK, 2) >> 8) << 30)), &ctrl->dlycfg1); in ddr2_ctrl_init()
185 ((RL + 3) << 28)), &ctrl->dlycfg2); in ddr2_ctrl_init()
190 &ctrl->dlycfg3); in ddr2_ctrl_init()
193 writel(0x0, &ctrl->odtcfg); in ddr2_ctrl_init()
194 writel(BIT(16), &ctrl->odtencfg); in ddr2_ctrl_init()
196 &ctrl->odtcfg); in ddr2_ctrl_init()
201 &ctrl->xfercfg); in ddr2_ctrl_init()
205 host_load_cmd(ctrl, 0, 0, IDLE_NOP, 400000); in ddr2_ctrl_init()
208 host_load_cmd(ctrl, 1, 0x04, PRECH_ALL_CMD, T_RP + T_CK); in ddr2_ctrl_init()
211 host_load_cmd(ctrl, 2, 0x200, LOAD_MODE_CMD, T_MRD_TCK * T_CK); in ddr2_ctrl_init()
214 host_load_cmd(ctrl, 3, 0x300, LOAD_MODE_CMD, T_MRD_TCK * T_CK); in ddr2_ctrl_init()
220 host_load_cmd(ctrl, 4, 0x100, in ddr2_ctrl_init()
227 host_load_cmd(ctrl, 5, temp, LOAD_MODE_CMD | (RL << 28) | (2 << 24), in ddr2_ctrl_init()
231 host_load_cmd(ctrl, 6, 4, PRECH_ALL_CMD, T_RP + T_CK); in ddr2_ctrl_init()
234 host_load_cmd(ctrl, 7, 0, REF_CMD, T_RFC_MIN); in ddr2_ctrl_init()
237 host_load_cmd(ctrl, 8, 0, REF_CMD, T_RFC_MIN); in ddr2_ctrl_init()
240 host_load_cmd(ctrl, 9, temp, LOAD_MODE_CMD | (RL << 28) | (3 << 24), in ddr2_ctrl_init()
244 host_load_cmd(ctrl, 10, 0x103, LOAD_MODE_CMD | (0xc << 24), in ddr2_ctrl_init()
248 host_load_cmd(ctrl, 11, 0x100, LOAD_MODE_CMD | (0x4 << 28), in ddr2_ctrl_init()
251 writel(CMD_VALID | NUMHOSTCMD(11), &ctrl->cmdissue); in ddr2_ctrl_init()
254 writel(INIT_START, &ctrl->memcon); in ddr2_ctrl_init()
257 wait_for_bit_le32(&ctrl->cmdissue, CMD_VALID, false, in ddr2_ctrl_init()
261 writel(INIT_START | INIT_DONE, &ctrl->memcon); in ddr2_ctrl_init()