Lines Matching refs:mac_reg
186 void *mac_reg; member
203 reg = readl(priv->mac_reg + SYS_RBUF_FLUSH_CTRL); in bcmgenet_umac_reset()
205 writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); in bcmgenet_umac_reset()
209 writel(reg, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); in bcmgenet_umac_reset()
212 writel(0, (priv->mac_reg + SYS_RBUF_FLUSH_CTRL)); in bcmgenet_umac_reset()
215 writel(0, priv->mac_reg + UMAC_CMD); in bcmgenet_umac_reset()
217 writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); in bcmgenet_umac_reset()
219 writel(0, priv->mac_reg + UMAC_CMD); in bcmgenet_umac_reset()
223 priv->mac_reg + UMAC_MIB_CTRL); in bcmgenet_umac_reset()
224 writel(0, priv->mac_reg + UMAC_MIB_CTRL); in bcmgenet_umac_reset()
226 writel(ENET_MAX_MTU_SIZE, priv->mac_reg + UMAC_MAX_FRAME_LEN); in bcmgenet_umac_reset()
229 reg = readl(priv->mac_reg + RBUF_CTRL); in bcmgenet_umac_reset()
231 writel(reg, (priv->mac_reg + RBUF_CTRL)); in bcmgenet_umac_reset()
233 writel(1, (priv->mac_reg + RBUF_TBUF_SIZE_CTRL)); in bcmgenet_umac_reset()
244 writel_relaxed(reg, priv->mac_reg + UMAC_MAC0); in bcmgenet_gmac_write_hwaddr()
247 writel_relaxed(reg, priv->mac_reg + UMAC_MAC1); in bcmgenet_gmac_write_hwaddr()
254 clrbits_32(priv->mac_reg + TDMA_REG_BASE + DMA_CTRL, DMA_EN); in bcmgenet_disable_dma()
255 clrbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, DMA_EN); in bcmgenet_disable_dma()
257 writel(1, priv->mac_reg + UMAC_TX_FLUSH); in bcmgenet_disable_dma()
259 writel(0, priv->mac_reg + UMAC_TX_FLUSH); in bcmgenet_disable_dma()
266 writel(dma_ctrl, priv->mac_reg + TDMA_REG_BASE + DMA_CTRL); in bcmgenet_enable_dma()
268 setbits_32(priv->mac_reg + RDMA_REG_BASE + DMA_CTRL, dma_ctrl); in bcmgenet_enable_dma()
280 prod_index = readl(priv->mac_reg + TDMA_PROD_INDEX); in bcmgenet_gmac_eth_send()
305 writel(prod_index, priv->mac_reg + TDMA_PROD_INDEX); in bcmgenet_gmac_eth_send()
308 cons = readl(priv->mac_reg + TDMA_CONS_INDEX); in bcmgenet_gmac_eth_send()
338 u32 prod_index = readl(priv->mac_reg + RDMA_PROD_INDEX); in bcmgenet_gmac_eth_recv()
370 writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); in bcmgenet_gmac_free_pkt()
400 priv->mac_reg + RDMA_REG_BASE + DMA_SCB_BURST_SIZE); in rx_ring_init()
402 writel(0x0, priv->mac_reg + RDMA_RING_REG_BASE + DMA_START_ADDR); in rx_ring_init()
403 writel(0x0, priv->mac_reg + RDMA_READ_PTR); in rx_ring_init()
404 writel(0x0, priv->mac_reg + RDMA_WRITE_PTR); in rx_ring_init()
406 priv->mac_reg + RDMA_RING_REG_BASE + DMA_END_ADDR); in rx_ring_init()
409 priv->c_index = readl(priv->mac_reg + RDMA_PROD_INDEX); in rx_ring_init()
410 writel(priv->c_index, priv->mac_reg + RDMA_CONS_INDEX); in rx_ring_init()
414 priv->mac_reg + RDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); in rx_ring_init()
415 writel(DMA_FC_THRESH_VALUE, priv->mac_reg + RDMA_XON_XOFF_THRESH); in rx_ring_init()
416 writel(1 << DEFAULT_Q, priv->mac_reg + RDMA_REG_BASE + DMA_RING_CFG); in rx_ring_init()
422 priv->mac_reg + TDMA_REG_BASE + DMA_SCB_BURST_SIZE); in tx_ring_init()
424 writel(0x0, priv->mac_reg + TDMA_RING_REG_BASE + DMA_START_ADDR); in tx_ring_init()
425 writel(0x0, priv->mac_reg + TDMA_READ_PTR); in tx_ring_init()
426 writel(0x0, priv->mac_reg + TDMA_WRITE_PTR); in tx_ring_init()
428 priv->mac_reg + TDMA_RING_REG_BASE + DMA_END_ADDR); in tx_ring_init()
430 priv->tx_index = readl(priv->mac_reg + TDMA_CONS_INDEX); in tx_ring_init()
431 writel(priv->tx_index, priv->mac_reg + TDMA_PROD_INDEX); in tx_ring_init()
433 writel(0x1, priv->mac_reg + TDMA_RING_REG_BASE + DMA_MBUF_DONE_THRESH); in tx_ring_init()
434 writel(0x0, priv->mac_reg + TDMA_FLOW_PERIOD); in tx_ring_init()
436 priv->mac_reg + TDMA_RING_REG_BASE + DMA_RING_BUF_SIZE); in tx_ring_init()
438 writel(1 << DEFAULT_Q, priv->mac_reg + TDMA_REG_BASE + DMA_RING_CFG); in tx_ring_init()
461 clrsetbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, OOB_DISABLE, in bcmgenet_adjust_link()
466 setbits_32(priv->mac_reg + EXT_RGMII_OOB_CTRL, ID_MODE_DIS); in bcmgenet_adjust_link()
468 writel(speed << CMD_SPEED_SHIFT, (priv->mac_reg + UMAC_CMD)); in bcmgenet_adjust_link()
478 priv->tx_desc_base = priv->mac_reg + GENET_TX_OFF; in bcmgenet_gmac_eth_start()
479 priv->rx_desc_base = priv->mac_reg + GENET_RX_OFF; in bcmgenet_gmac_eth_start()
511 setbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); in bcmgenet_gmac_eth_start()
541 setbits_32(priv->mac_reg + MDIO_CMD, MDIO_START_BUSY); in bcmgenet_mdio_start()
554 writel_relaxed(val, priv->mac_reg + MDIO_CMD); in bcmgenet_mdio_write()
559 return wait_for_bit_32(priv->mac_reg + MDIO_CMD, in bcmgenet_mdio_write()
572 writel_relaxed(val, priv->mac_reg + MDIO_CMD); in bcmgenet_mdio_read()
577 ret = wait_for_bit_32(priv->mac_reg + MDIO_CMD, in bcmgenet_mdio_read()
582 val = readl_relaxed(priv->mac_reg + MDIO_CMD); in bcmgenet_mdio_read()
612 writel(PORT_MODE_EXT_GPHY, priv->mac_reg + SYS_PORT_CTRL); in bcmgenet_interface_set()
632 priv->mac_reg = map_physmem(pdata->iobase, SZ_64K, MAP_NOCACHE); in bcmgenet_eth_probe()
637 reg = readl_relaxed(priv->mac_reg + SYS_REV_CTRL); in bcmgenet_eth_probe()
653 writel(0, priv->mac_reg + SYS_RBUF_FLUSH_CTRL); in bcmgenet_eth_probe()
656 writel(0, priv->mac_reg + UMAC_CMD); in bcmgenet_eth_probe()
658 writel(CMD_SW_RESET | CMD_LCL_LOOP_EN, priv->mac_reg + UMAC_CMD); in bcmgenet_eth_probe()
676 clrbits_32(priv->mac_reg + UMAC_CMD, CMD_TX_EN | CMD_RX_EN); in bcmgenet_gmac_eth_stop()