Lines Matching refs:regmap_write
219 regmap_write(miig_rt, offset, val); in rx_class_ft1_set_start_len()
228 regmap_write(miig_rt, offset, addr_to_da0(addr)); in rx_class_ft1_set_da()
230 regmap_write(miig_rt, offset, addr_to_da1(addr)); in rx_class_ft1_set_da()
239 regmap_write(miig_rt, offset, addr_to_da0(addr)); in rx_class_ft1_set_da_mask()
241 regmap_write(miig_rt, offset, addr_to_da1(addr)); in rx_class_ft1_set_da_mask()
270 regmap_write(miig_rt, offset, data); in rx_class_set_and()
279 regmap_write(miig_rt, offset, data); in rx_class_set_or()
284 regmap_write(miig_rt, MAC_INTERFACE_0, addr_to_da0(mac)); in icssg_class_set_host_mac_addr()
285 regmap_write(miig_rt, MAC_INTERFACE_1, addr_to_da1(mac)); in icssg_class_set_host_mac_addr()
290 regmap_write(miig_rt, offs[slice].mac0, addr_to_da0(mac)); in icssg_class_set_mac_addr()
291 regmap_write(miig_rt, offs[slice].mac1, addr_to_da1(mac)); in icssg_class_set_mac_addr()
313 regmap_write(miig_rt, offset, data); in icssg_class_disable_n()
339 regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0); in icssg_class_disable()
364 regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0); in icssg_class_default()