Lines Matching refs:dm_i2c_reg_write
219 dm_i2c_reg_write(dev, TOPCFG4, 0x30); in dp501_sw_init()
221 dm_i2c_reg_write(dev, TOPCFG4, 0x0c); in dp501_sw_init()
222 dm_i2c_reg_write(dev, 0x8f, 0x02); in dp501_sw_init()
239 dm_i2c_reg_write(priv->chip2, SEL_PIO1, 0x02); in dp501_sw_init()
240 dm_i2c_reg_write(priv->chip2, SEL_PIO2, 0x04); in dp501_sw_init()
241 dm_i2c_reg_write(priv->chip2, SEL_PIO3, 0x10); in dp501_sw_init()
243 dm_i2c_reg_write(dev, LINK_STATE_CTRL, 0xa0); in dp501_sw_init()
244 dm_i2c_reg_write(dev, 0x8f, 0x02); in dp501_sw_init()
245 dm_i2c_reg_write(dev, TOPCFG1, 0x16); in dp501_sw_init()
246 dm_i2c_reg_write(dev, TOPCFG0, 0x24); in dp501_sw_init()
247 dm_i2c_reg_write(dev, HPD2_IRQ_CTRL, 0x30); in dp501_sw_init()
248 dm_i2c_reg_write(dev, AUXIRQ_CTRL, 0xff); in dp501_sw_init()
249 dm_i2c_reg_write(dev, LINK_IRQ, 0xff); in dp501_sw_init()
252 dm_i2c_reg_write(dev, VCAPCTRL3, 0x30); in dp501_sw_init()
255 dm_i2c_reg_write(dev, LINK_CTRL0, 0x82); in dp501_sw_init()
257 dm_i2c_reg_write(dev, VCAPCTRL4, 0x07); in dp501_sw_init()
258 dm_i2c_reg_write(dev, AUX_RETRY_CTRL, 0x7f); in dp501_sw_init()
259 dm_i2c_reg_write(dev, TIMEOUT_CTRL, 0x1e); in dp501_sw_init()
260 dm_i2c_reg_write(dev, AUXCTL_REG, 0x06); in dp501_sw_init()
263 dm_i2c_reg_write(dev, HPDCTL0, 0xa9); in dp501_sw_init()
266 dm_i2c_reg_write(dev, QUALTEST_CTL, 0x00); in dp501_sw_init()
268 dm_i2c_reg_write(dev, 0x8f, 0x02); in dp501_sw_init()
270 dm_i2c_reg_write(dev, VCAPCTRL0, 0xc4); in dp501_sw_init()
273 dm_i2c_reg_write(dev, MISC0, 0x20); in dp501_sw_init()
275 dm_i2c_reg_write(dev, VCAPCPCTL2, 0x01); in dp501_sw_init()
297 dm_i2c_reg_write(dev, DPCD_ADDR_L, (u8)(config >> 8)); in dpcd_configure()
298 dm_i2c_reg_write(dev, DPCD_ADDR_M, (u8)(config >> 16)); in dpcd_configure()
299 dm_i2c_reg_write(dev, DPCD_ADDR_H, (u8)((config >> 24) | BIT(7))); in dpcd_configure()
300 dm_i2c_reg_write(dev, DPCD_LENGTH, 0x00); in dpcd_configure()
301 dm_i2c_reg_write(dev, LINK_IRQ, 0x20); in dpcd_configure()
304 dm_i2c_reg_write(dev, DPCD_WDATA, (u8)(config & 0xff)); in dpcd_configure()
306 dm_i2c_reg_write(dev, DPCD_CTL, 0x01); in dpcd_configure()
360 dm_i2c_reg_write(dev, TRAINING_CTL, 0x00); in dp501_reset_link()
361 dm_i2c_reg_write(dev, SWRST, 0xf8); in dp501_reset_link()
362 dm_i2c_reg_write(dev, SWRST, 0x00); in dp501_reset_link()
391 dm_i2c_reg_write(dev, LINK_BW, link); in dp501_link_training()
392 dm_i2c_reg_write(dev, LANE_CNT, lane | BIT(7)); in dp501_link_training()
407 dm_i2c_reg_write(dev, LINK_STATE_CTRL, 0x00); in dp501_link_training()
408 dm_i2c_reg_write(dev, TRAINING_CTL, 0x0d); in dp501_link_training()
415 dm_i2c_reg_write(dev, LINK_IRQ, 0xff); in dp501_link_training()