Lines Matching refs:value
69 u32 value; in tegra_dc_enable_controller() local
71 value = readl(&dc->disp.disp_win_opt); in tegra_dc_enable_controller()
72 value |= DSI_ENABLE; in tegra_dc_enable_controller()
73 writel(value, &dc->disp.disp_win_opt); in tegra_dc_enable_controller()
106 u32 value; in tegra_dsi_read_response() local
109 value = readl(&misc->dsi_rd_data); in tegra_dsi_read_response()
111 switch (value & 0x3f) { in tegra_dsi_read_response()
113 errors = (value >> 8) & 0xffff; in tegra_dsi_read_response()
123 rx[0] = (value >> 8) & 0xff; in tegra_dsi_read_response()
128 rx[0] = (value >> 8) & 0xff; in tegra_dsi_read_response()
129 rx[1] = (value >> 16) & 0xff; in tegra_dsi_read_response()
134 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); in tegra_dsi_read_response()
138 size = ((value >> 8) & 0xff00) | ((value >> 8) & 0xff); in tegra_dsi_read_response()
143 __func__, value & 0x3f); in tegra_dsi_read_response()
153 value = readl(&misc->dsi_rd_data); in tegra_dsi_read_response()
156 rx[j + k] = (value >> (k << 3)) & 0xff; in tegra_dsi_read_response()
169 u32 value = readl(&misc->dsi_trigger); in tegra_dsi_transmit() local
171 if ((value & DSI_TRIGGER_HOST) == 0) in tegra_dsi_transmit()
185 u32 value = readl(&misc->dsi_status); in tegra_dsi_wait_for_response() local
186 u8 count = value & 0x1f; in tegra_dsi_wait_for_response()
203 u32 value; in tegra_dsi_writesl() local
206 value = 0; in tegra_dsi_writesl()
209 value |= buf[j + i] << (i << 3); in tegra_dsi_writesl()
211 writel(value, &misc->dsi_wr_data); in tegra_dsi_writesl()
225 u32 value; in tegra_dsi_host_transfer() local
238 value = readl(&misc->dsi_status); in tegra_dsi_host_transfer()
239 if (value & (DSI_STATUS_UNDERFLOW | DSI_STATUS_OVERFLOW)) { in tegra_dsi_host_transfer()
240 value = DSI_HOST_CONTROL_FIFO_RESET; in tegra_dsi_host_transfer()
241 writel(value, &misc->host_dsi_ctrl); in tegra_dsi_host_transfer()
245 value = readl(&misc->dsi_pwr_ctrl); in tegra_dsi_host_transfer()
246 value |= DSI_POWER_CONTROL_ENABLE; in tegra_dsi_host_transfer()
247 writel(value, &misc->dsi_pwr_ctrl); in tegra_dsi_host_transfer()
251 value = DSI_HOST_CONTROL_CRC_RESET | DSI_HOST_CONTROL_TX_TRIG_HOST | in tegra_dsi_host_transfer()
255 value |= DSI_HOST_CONTROL_HS; in tegra_dsi_host_transfer()
262 value |= DSI_HOST_CONTROL_FIFO_SEL; in tegra_dsi_host_transfer()
264 writel(value, &misc->host_dsi_ctrl); in tegra_dsi_host_transfer()
272 value = readl(&misc->host_dsi_ctrl); in tegra_dsi_host_transfer()
273 value |= DSI_HOST_CONTROL_PKT_BTA; in tegra_dsi_host_transfer()
274 writel(value, &misc->host_dsi_ctrl); in tegra_dsi_host_transfer()
277 value = DSI_CONTROL_LANES(0) | DSI_CONTROL_HOST_ENABLE; in tegra_dsi_host_transfer()
278 writel(value, &misc->dsi_ctrl); in tegra_dsi_host_transfer()
281 value = header[2] << 16 | header[1] << 8 | header[0]; in tegra_dsi_host_transfer()
282 writel(value, &misc->dsi_wr_data); in tegra_dsi_host_transfer()
301 value = readl(&misc->dsi_rd_data); in tegra_dsi_host_transfer()
302 switch (value) { in tegra_dsi_host_transfer()
312 printf("%s: unknown status: %08x\n", __func__, value); in tegra_dsi_host_transfer()
491 u32 value; in tegra_dsi_pad_calibrate() local
494 value = DSI_PAD_CONTROL_PAD_LPUPADJ(0x1) | in tegra_dsi_pad_calibrate()
502 writel(value, &pad->pad_ctrl); in tegra_dsi_pad_calibrate()
510 value = MIPI_CAL_TERMOSA(0x4); in tegra_dsi_pad_calibrate()
511 writel(value, TEGRA_VI_BASE + (CSI_CILA_MIPI_CAL_CONFIG_0 << 2)); in tegra_dsi_pad_calibrate()
513 value = MIPI_CAL_TERMOSB(0x4); in tegra_dsi_pad_calibrate()
514 writel(value, TEGRA_VI_BASE + (CSI_CILB_MIPI_CAL_CONFIG_0 << 2)); in tegra_dsi_pad_calibrate()
516 value = MIPI_CAL_HSPUOSD(0x3) | MIPI_CAL_HSPDOSD(0x4); in tegra_dsi_pad_calibrate()
517 writel(value, TEGRA_VI_BASE + (CSI_DSI_MIPI_CAL_CONFIG << 2)); in tegra_dsi_pad_calibrate()
519 value = PAD_DRIV_DN_REF(0x5) | PAD_DRIV_UP_REF(0x7); in tegra_dsi_pad_calibrate()
520 writel(value, TEGRA_VI_BASE + (CSI_MIPIBIAS_PAD_CONFIG << 2)); in tegra_dsi_pad_calibrate()
522 value = PAD_CIL_PDVREG(0x0); in tegra_dsi_pad_calibrate()
523 writel(value, TEGRA_VI_BASE + (CSI_CIL_PAD_CONFIG << 2)); in tegra_dsi_pad_calibrate()
530 u32 value; in tegra_dsi_mipi_calibrate() local
545 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0); in tegra_dsi_mipi_calibrate()
546 writel(value, &pad->pad_ctrl); in tegra_dsi_mipi_calibrate()
548 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) | in tegra_dsi_mipi_calibrate()
551 writel(value, &pad->pad_ctrl_2); in tegra_dsi_mipi_calibrate()
553 value = DSI_PAD_PREEMP_PD_CLK(0x3) | DSI_PAD_PREEMP_PU_CLK(0x3) | in tegra_dsi_mipi_calibrate()
555 writel(value, &pad->pad_ctrl_3); in tegra_dsi_mipi_calibrate()
572 u32 value; in tegra_dsi_set_timeout() local
576 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout); in tegra_dsi_set_timeout()
577 writel(value, &rtimeout->dsi_timeout_0); in tegra_dsi_set_timeout()
581 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000); in tegra_dsi_set_timeout()
582 writel(value, &rtimeout->dsi_timeout_1); in tegra_dsi_set_timeout()
584 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0); in tegra_dsi_set_timeout()
585 writel(value, &rtimeout->dsi_to_tally); in tegra_dsi_set_timeout()
597 u32 value; in tegra_dsi_set_phy_timing() local
599 value = DSI_TIMING_FIELD(dphy_timing->hsexit, period, 1) << 24 | in tegra_dsi_set_phy_timing()
603 writel(value, &ptiming->dsi_phy_timing_0); in tegra_dsi_set_phy_timing()
605 value = DSI_TIMING_FIELD(dphy_timing->clktrail, period, 1) << 24 | in tegra_dsi_set_phy_timing()
609 writel(value, &ptiming->dsi_phy_timing_1); in tegra_dsi_set_phy_timing()
611 value = DSI_TIMING_FIELD(dphy_timing->clkprepare, period, 1) << 16 | in tegra_dsi_set_phy_timing()
614 writel(value, &ptiming->dsi_phy_timing_2); in tegra_dsi_set_phy_timing()
616 value = DSI_TIMING_FIELD(dphy_timing->taget, period, 1) << 16 | in tegra_dsi_set_phy_timing()
619 writel(value, &ptiming->dsi_bta_timing); in tegra_dsi_set_phy_timing()
671 u32 value; in tegra_dsi_configure() local
686 value = DSI_CONTROL_CHANNEL(0) | in tegra_dsi_configure()
690 writel(value, &misc->dsi_ctrl); in tegra_dsi_configure()
694 value = DSI_HOST_CONTROL_HS; in tegra_dsi_configure()
695 writel(value, &misc->host_dsi_ctrl); in tegra_dsi_configure()
697 value = readl(&misc->dsi_ctrl); in tegra_dsi_configure()
700 value |= DSI_CONTROL_HS_CLK_CTRL; in tegra_dsi_configure()
702 value &= ~DSI_CONTROL_TX_TRIG(3); in tegra_dsi_configure()
706 value &= ~DSI_CONTROL_DCS_ENABLE; in tegra_dsi_configure()
708 value |= DSI_CONTROL_DCS_ENABLE; in tegra_dsi_configure()
710 value |= DSI_CONTROL_VIDEO_ENABLE; in tegra_dsi_configure()
711 value &= ~DSI_CONTROL_HOST_ENABLE; in tegra_dsi_configure()
712 writel(value, &misc->dsi_ctrl); in tegra_dsi_configure()
754 value = 1 + (timing->hactive.typ / 2) * mul / div; in tegra_dsi_configure()
757 value = 1 + timing->hactive.typ * mul / div; in tegra_dsi_configure()
761 writel(value << 16, &len->dsi_pkt_len_2_3); in tegra_dsi_configure()
762 writel(value << 16, &len->dsi_pkt_len_4_5); in tegra_dsi_configure()
765 value = MIPI_DCS_WRITE_MEMORY_START << 8 | in tegra_dsi_configure()
767 writel(value, &len->dsi_dcs_cmds); in tegra_dsi_configure()
785 value = bclk - bclk_ganged + delay + 20; in tegra_dsi_configure()
788 value = 8 * mul / div; in tegra_dsi_configure()
791 writel(value, &misc->dsi_sol_delay); in tegra_dsi_configure()
809 u32 value; in tegra_dsi_enable() local
812 value = readl(&misc->dsi_pwr_ctrl); in tegra_dsi_enable()
813 value |= DSI_POWER_CONTROL_ENABLE; in tegra_dsi_enable()
814 writel(value, &misc->dsi_pwr_ctrl); in tegra_dsi_enable()
829 u32 value, lanes; in tegra_dsi_encoder_enable() local
836 value = readl(&misc->dsi_pwr_ctrl); in tegra_dsi_encoder_enable()
838 if (value & DSI_POWER_CONTROL_ENABLE) { in tegra_dsi_encoder_enable()
839 value = readl(&misc->dsi_pwr_ctrl); in tegra_dsi_encoder_enable()
840 value &= ~DSI_POWER_CONTROL_ENABLE; in tegra_dsi_encoder_enable()
841 writel(value, &misc->dsi_pwr_ctrl); in tegra_dsi_encoder_enable()