Lines Matching refs:uint8_t
295 uint8_t info_size_crc; /* 0 # bytes */
296 uint8_t spd_rev; /* 1 Total # bytes of SPD */
297 uint8_t mem_type; /* 2 Key Byte / mem type */
298 uint8_t module_type; /* 3 Key Byte / Module Type */
299 uint8_t density_banks; /* 4 Density and Banks */
300 uint8_t addressing; /* 5 Addressing */
301 uint8_t package_type; /* 6 Package type */
302 uint8_t opt_feature; /* 7 Optional features */
303 uint8_t thermal_ref; /* 8 Thermal and refresh */
304 uint8_t oth_opt_features; /* 9 Other optional features */
305 uint8_t res_10; /* 10 Reserved */
306 uint8_t module_vdd; /* 11 Module nominal voltage */
307 uint8_t organization; /* 12 Module Organization */
308 uint8_t bus_width; /* 13 Module Memory Bus Width */
309 uint8_t therm_sensor; /* 14 Module Thermal Sensor */
310 uint8_t ext_type; /* 15 Extended module type */
311 uint8_t res_16;
312 uint8_t timebases; /* 17 MTb and FTB */
313 uint8_t tck_min; /* 18 tCKAVGmin */
314 uint8_t tck_max; /* 19 TCKAVGmax */
315 uint8_t caslat_b1; /* 20 CAS latencies, 1st byte */
316 uint8_t caslat_b2; /* 21 CAS latencies, 2nd byte */
317 uint8_t caslat_b3; /* 22 CAS latencies, 3rd byte */
318 uint8_t caslat_b4; /* 23 CAS latencies, 4th byte */
319 uint8_t taa_min; /* 24 Min CAS Latency Time */
320 uint8_t trcd_min; /* 25 Min RAS# to CAS# Delay Time */
321 uint8_t trp_min; /* 26 Min Row Precharge Delay Time */
322 uint8_t tras_trc_ext; /* 27 Upper Nibbles for tRAS and tRC */
323 uint8_t tras_min_lsb; /* 28 tRASmin, lsb */
324 uint8_t trc_min_lsb; /* 29 tRCmin, lsb */
325 uint8_t trfc1_min_lsb; /* 30 Min Refresh Recovery Delay Time */
326 uint8_t trfc1_min_msb; /* 31 Min Refresh Recovery Delay Time */
327 uint8_t trfc2_min_lsb; /* 32 Min Refresh Recovery Delay Time */
328 uint8_t trfc2_min_msb; /* 33 Min Refresh Recovery Delay Time */
329 uint8_t trfc4_min_lsb; /* 34 Min Refresh Recovery Delay Time */
330 uint8_t trfc4_min_msb; /* 35 Min Refresh Recovery Delay Time */
331 uint8_t tfaw_msb; /* 36 Upper Nibble for tFAW */
332 uint8_t tfaw_min; /* 37 tFAW, lsb */
333 uint8_t trrds_min; /* 38 tRRD_Smin, MTB */
334 uint8_t trrdl_min; /* 39 tRRD_Lmin, MTB */
335 uint8_t tccdl_min; /* 40 tCCS_Lmin, MTB */
336 uint8_t res_41[60-41]; /* 41 Rserved */
337 uint8_t mapping[78-60]; /* 60~77 Connector to SDRAM bit map */
338 uint8_t res_78[117-78]; /* 78~116, Reserved */
349 uint8_t crc[2]; /* 126-127 SPD CRC */
355 uint8_t mod_height;
357 uint8_t mod_thickness;
359 uint8_t ref_raw_card;
362 uint8_t addr_mapping;
364 uint8_t res_132[254-132];
366 uint8_t crc[2];
370 uint8_t mod_height;
372 uint8_t mod_thickness;
374 uint8_t ref_raw_card;
376 uint8_t modu_attr;
378 uint8_t thermal;
380 uint8_t reg_id_lo;
382 uint8_t reg_id_hi;
384 uint8_t reg_rev;
392 uint8_t crc[2];
396 uint8_t mod_height;
398 uint8_t mod_thickness;
400 uint8_t ref_raw_card;
402 uint8_t modu_attr;
404 uint8_t thermal;
406 uint8_t reg_id_lo;
408 uint8_t reg_id_hi;
410 uint8_t reg_rev;
412 uint8_t reg_map;
414 uint8_t reg_drv;
416 uint8_t reg_drv_ck;
418 uint8_t data_buf_rev;
420 uint8_t vrefqe_r0;
422 uint8_t vrefqe_r1;
424 uint8_t vrefqe_r2;
426 uint8_t vrefqe_r3;
428 uint8_t data_intf;
433 uint8_t data_drv_1866;
438 uint8_t data_drv_2400;
443 uint8_t data_drv_3200;
445 uint8_t dram_drv;
450 uint8_t dram_odt_1866;
455 uint8_t dram_odt_2400;
460 uint8_t dram_odt_3200;
465 uint8_t dram_odt_park_1866;
470 uint8_t dram_odt_park_2400;
475 uint8_t dram_odt_park_3200;
476 uint8_t res_155[254-155]; /* Reserved */
478 uint8_t crc[2];
480 uint8_t uc[128]; /* 128-255 Module-Specific Section */
483 uint8_t res_256[320-256]; /* 256~319 Reserved */
486 uint8_t mmid_lsb; /* 320 Module MfgID Code LSB */
487 uint8_t mmid_msb; /* 321 Module MfgID Code MSB */
488 uint8_t mloc; /* 322 Mfg Location */
489 uint8_t mdate[2]; /* 323~324 Mfg Date */
490 uint8_t sernum[4]; /* 325~328 Module Serial Number */
491 uint8_t mpart[20]; /* 329~348 Mfg's Module Part Number */
492 uint8_t mrev; /* 349 Module Revision Code */
493 uint8_t dmid_lsb; /* 350 DRAM MfgID Code LSB */
494 uint8_t dmid_msb; /* 351 DRAM MfgID Code MSB */
495 uint8_t stepping; /* 352 DRAM stepping */
496 uint8_t msd[29]; /* 353~381 Mfg's Specific Data */
497 uint8_t res_382[2]; /* 382~383 Reserved */
499 uint8_t user[512-384]; /* 384~511 End User Programmable */