Lines Matching refs:BIT
38 #define CLK_SET_RATE_GATE BIT(0) /* must be gated across rate change */
39 #define CLK_SET_PARENT_GATE BIT(1) /* must be gated across re-parent */
40 #define CLK_SET_RATE_PARENT BIT(2) /* propagate rate change up one level */
41 #define CLK_IGNORE_UNUSED BIT(3) /* do not gate even if unused */
43 #define CLK_IS_BASIC BIT(5) /* Basic clk, can't do a to_clk_foo() */
44 #define CLK_GET_RATE_NOCACHE BIT(6) /* do not use the cached clk rate */
45 #define CLK_SET_RATE_NO_REPARENT BIT(7) /* don't re-parent on rate change */
46 #define CLK_GET_ACCURACY_NOCACHE BIT(8) /* do not use the cached clk accuracy */
47 #define CLK_RECALC_NEW_RATES BIT(9) /* recalc rates after notifications */
48 #define CLK_SET_RATE_UNGATE BIT(10) /* clock needs to run to set rate */
49 #define CLK_IS_CRITICAL BIT(11) /* do not gate, ever */
51 #define CLK_OPS_PARENT_ENABLE BIT(12)
53 #define CLK_DUTY_CYCLE_PARENT BIT(13)
55 #define CLK_MUX_INDEX_ONE BIT(0)
56 #define CLK_MUX_INDEX_BIT BIT(1)
57 #define CLK_MUX_HIWORD_MASK BIT(2)
58 #define CLK_MUX_READ_ONLY BIT(3) /* mux can't be changed */
59 #define CLK_MUX_ROUND_CLOSEST BIT(4)
111 #define CLK_GATE_SET_TO_DISABLE BIT(0)
112 #define CLK_GATE_HIWORD_MASK BIT(1)
140 #define CLK_DIVIDER_ONE_BASED BIT(0)
141 #define CLK_DIVIDER_POWER_OF_TWO BIT(1)
142 #define CLK_DIVIDER_ALLOW_ZERO BIT(2)
143 #define CLK_DIVIDER_HIWORD_MASK BIT(3)
144 #define CLK_DIVIDER_ROUND_CLOSEST BIT(4)
145 #define CLK_DIVIDER_READ_ONLY BIT(5)
146 #define CLK_DIVIDER_MAX_AT_ZERO BIT(6)