Lines Matching refs:u16
78 u16 ceter; /* QE timer event register */
80 u16 cetmr; /* QE timers mask register */
87 u16 cercr; /* QE RAM control register */
90 u16 ceexe1; /* QE external request 1 event register */
92 u16 ceexm1; /* QE external request 1 mask register */
94 u16 ceexe2; /* QE external request 2 event register */
96 u16 ceexm2; /* QE external request 2 mask register */
98 u16 ceexe3; /* QE external request 3 event register */
100 u16 ceexm3; /* QE external request 3 mask register */
102 u16 ceexe4; /* QE external request 4 event register */
104 u16 ceexm4; /* QE external request 4 mask register */
129 u16 gtmdr1; /* Timer 1 mode register */
130 u16 gtmdr2; /* Timer 2 mode register */
131 u16 gtrfr1; /* Timer 1 reference register */
132 u16 gtrfr2; /* Timer 2 reference register */
133 u16 gtcpr1; /* Timer 1 capture register */
134 u16 gtcpr2; /* Timer 2 capture register */
135 u16 gtcnr1; /* Timer 1 counter */
136 u16 gtcnr2; /* Timer 2 counter */
137 u16 gtmdr3; /* Timer 3 mode register */
138 u16 gtmdr4; /* Timer 4 mode register */
139 u16 gtrfr3; /* Timer 3 reference register */
140 u16 gtrfr4; /* Timer 4 reference register */
141 u16 gtcpr3; /* Timer 3 capture register */
142 u16 gtcpr4; /* Timer 4 capture register */
143 u16 gtcnr3; /* Timer 3 counter */
144 u16 gtcnr4; /* Timer 4 counter */
145 u16 gtevr1; /* Timer 1 event register */
146 u16 gtevr2; /* Timer 2 event register */
147 u16 gtevr3; /* Timer 3 event register */
148 u16 gtevr4; /* Timer 4 event register */
149 u16 gtps; /* Timer 1 prescale register */
194 u16 siamr1; /* SI1 TDMA mode register */
195 u16 sibmr1; /* SI1 TDMB mode register */
196 u16 sicmr1; /* SI1 TDMC mode register */
197 u16 sidmr1; /* SI1 TDMD mode register */
204 u16 sirsr1_h; /* SI1 RAM shadow address register high */
214 u16 siemr1; /* SI1 TDME mode register 16 bits */
215 u16 sifmr1; /* SI1 TDMF mode register 16 bits */
216 u16 sigmr1; /* SI1 TDMG mode register 16 bits */
217 u16 sihmr1; /* SI1 TDMH mode register 16 bits */
224 u16 sirsr1_l; /* SI1 RAM shadow address register low 16 bits */
252 u16 usb_usep1;
253 u16 usb_usep2;
254 u16 usb_usep3;
255 u16 usb_usep4;
257 u16 usb_usber;
259 u16 usb_usbmr;
262 u16 usb_ussft;
264 u16 usb_usfrn;
281 u16 upsmr; /* UCCx protocol-specific mode register */
283 u16 utodr; /* UCCx transmit on demand register */
284 u16 udsr; /* UCCx data synchronization register */
285 u16 ucce; /* UCCx event register */
287 u16 uccm; /* UCCx mask register */
291 u16 utpt;
326 u16 uescr; /* UCC Ethernet statistics control reg */
355 u16 txcf; /* Total number of PAUSE control frames
385 u16 utodr; /* UCCx transmit on demand register */
387 u16 udsr; /* UCCx data synchronization register */
394 u16 urfs; /* UCC receive FIFO size */
396 u16 urfet; /* UCC receive FIFO emergency threshold */
397 u16 urfset; /* UCC receive FIFO special emergency
400 u16 utfs; /* UCC transmit FIFO size */
402 u16 utfet; /* UCC transmit FIFO emergency threshold */
404 u16 utftt; /* UCC transmit FIFO transmit threshold */
406 u16 utpt; /* UCC transmit polling timer */
458 u16 uprp1;
459 u16 uprp2;
460 u16 uprp3;
461 u16 uprp4;
463 u16 uptirr1_0; /* Device 1 transmit internal rate 0 */
464 u16 uptirr1_1; /* Device 1 transmit internal rate 1 */
465 u16 uptirr1_2; /* Device 1 transmit internal rate 2 */
466 u16 uptirr1_3; /* Device 1 transmit internal rate 3 */
467 u16 uptirr2_0; /* Device 2 transmit internal rate 0 */
468 u16 uptirr2_1; /* Device 2 transmit internal rate 1 */
469 u16 uptirr2_2; /* Device 2 transmit internal rate 2 */
470 u16 uptirr2_3; /* Device 2 transmit internal rate 3 */
471 u16 uptirr3_0; /* Device 3 transmit internal rate 0 */
472 u16 uptirr3_1; /* Device 3 transmit internal rate 1 */
473 u16 uptirr3_2; /* Device 3 transmit internal rate 2 */
474 u16 uptirr3_3; /* Device 3 transmit internal rate 3 */
475 u16 uptirr4_0; /* Device 4 transmit internal rate 0 */
476 u16 uptirr4_1; /* Device 4 transmit internal rate 1 */
477 u16 uptirr4_2; /* Device 4 transmit internal rate 2 */
478 u16 uptirr4_3; /* Device 4 transmit internal rate 3 */