1if CPU_V7A
2
3config CPU_V7_HAS_NONSEC
4        bool
5
6config CPU_V7_HAS_VIRT
7        bool
8
9config ARCH_SUPPORT_PSCI
10        bool
11
12config ARMV7_NONSEC
13	bool "Enable support for booting in non-secure mode" if EXPERT
14	depends on CPU_V7_HAS_NONSEC
15	default y
16	---help---
17	Say Y here to enable support for booting in non-secure / SVC mode.
18
19config ARMV7_BOOT_SEC_DEFAULT
20	bool "Boot in secure mode by default" if EXPERT
21	depends on ARMV7_NONSEC
22	default y if ARCH_TEGRA
23	---help---
24	Say Y here to boot in secure mode by default even if non-secure mode
25	is supported. This option is useful to boot kernels which do not
26	suppport booting in non-secure mode. Only set this if you need it.
27	This can be overridden at run-time by setting the bootm_boot_mode env.
28	variable to "sec" or "nonsec".
29
30config HAS_ARMV7_SECURE_BASE
31	bool "Enable support for a ahardware secure memory area"
32	default y if ARCH_LS1021A || ARCH_MX7 || ARCH_MX7ULP || ARCH_STM32MP \
33			|| MACH_SUN6I || MACH_SUN7I || MACH_SUN8I || TEGRA124
34
35config ARMV7_SECURE_BASE
36	hex "Base address for secure mode memory"
37	depends on HAS_ARMV7_SECURE_BASE
38	default 0xfff00000 if TEGRA124
39	default 0x2ffe0000 if STM32MP13X
40	default 0x2ffc0000 if STM32MP15X
41	default 0x2f000000 if ARCH_MX7ULP
42	default 0x10010000 if ARCH_LS1021A
43	default 0x00900000 if ARCH_MX7
44	default 0x00044000 if MACH_SUN8I
45	default 0x00020000 if MACH_SUN6I || MACH_SUN7I
46
47config ARMV7_SECURE_RESERVE_SIZE
48	hex
49	depends on TEGRA124 && HAS_ARMV7_SECURE_BASE
50	default 0x100000
51	help
52	  Reserve top 1M for secure RAM
53
54config ARMV7_SECURE_MAX_SIZE
55	hex
56	depends on ARMV7_SECURE_BASE && ARCH_STM32MP || MACH_SUN6I \
57			|| MACH_SUN7I || MACH_SUN8I
58	default 0xbc00 if MACH_SUN8I && !MACH_SUN8I_H3
59	default 0x3c00 if MACH_SUN8I && MACH_SUN8I_H3
60	default 0x10000
61
62config ARM_GIC_BASE_ADDRESS
63	hex
64	depends on ARMV7_NONSEC
65	depends on ARCH_EXYNOS5 || MACH_SUN8I_R528
66	default 0x10480000 if ARCH_EXYNOS5
67	default 0x03020000 if MACH_SUN8I_R528
68	help
69	  Override the GIC base address if the Arm Cortex defined
70	  CBAR/PERIPHBASE system register holds the wrong value.
71	  Used by the PSCI code to configure the secure side of the GIC.
72
73config ARMV7_VIRT
74	bool "Enable support for hardware virtualization" if EXPERT
75	depends on CPU_V7_HAS_VIRT && ARMV7_NONSEC
76	default y
77	---help---
78	Say Y here to boot in hypervisor (HYP) mode when booting non-secure.
79
80config ARMV7_PSCI
81	bool "Enable PSCI support" if EXPERT
82	depends on ARMV7_NONSEC && ARCH_SUPPORT_PSCI
83	default y
84	help
85	  Say Y here to enable PSCI support.
86
87choice
88	prompt "Supported PSCI version"
89	depends on ARMV7_PSCI
90	default ARMV7_PSCI_0_1 if ARCH_SUNXI
91	default ARMV7_PSCI_1_0
92	help
93	  Select the supported PSCI version.
94
95config ARMV7_PSCI_1_0
96	bool "PSCI V1.0"
97
98config ARMV7_PSCI_0_2
99	bool "PSCI V0.2"
100
101config ARMV7_PSCI_0_1
102	bool "PSCI V0.1"
103endchoice
104
105config ARMV7_PSCI_NR_CPUS
106	int "Maximum supported CPUs for PSCI"
107	depends on ARMV7_NONSEC
108	default 4
109	help
110	  The maximum number of CPUs supported in the PSCI firmware.
111	  It is no problem to set a larger value than the number of
112	  CPUs in the actual hardware implementation.
113
114config ARMV7_LPAE
115	bool "Use LPAE page table format" if EXPERT
116	depends on CPU_V7A
117	default y if ARMV7_VIRT
118	---help---
119	Say Y here to use the long descriptor page table format. This is
120	required if U-Boot runs in HYP mode.
121
122config ARMV7_SET_CORTEX_SMPEN
123	bool
124	help
125	  Enable the ARM Cortex ACTLR.SMP enable bit in U-Boot.
126
127config SPL_ARMV7_SET_CORTEX_SMPEN
128	bool
129	help
130	  Enable the ARM Cortex ACTLR.SMP enable bit on SPL startup.
131
132endif
133