1
2config BITBANGMII
3	bool "Bit-banged ethernet MII management channel support"
4
5config MV88E6352_SWITCH
6	bool "Marvell 88E6352 switch support"
7
8menuconfig PHYLIB
9	bool "Ethernet PHY (physical media interface) support"
10	depends on NET || NET_LWIP
11	help
12	  Enable Ethernet PHY (physical media interface) support.
13
14if PHYLIB
15
16config PHY_ADDR_ENABLE
17	bool "Limit phy address"
18	default y if ARCH_SUNXI
19	help
20	  Select this if you want to control which phy address is used
21
22config PHY_ANEG_TIMEOUT
23	int "PHY auto-negotiation timeout"
24	default 4000
25	help
26	  Value of PHY auto-negotiation timeout with the base being
27	  "decimal" and the unit being "millisecond". This can be
28	  overridden by the "phy_aneg_timeout" environment variable
29	  that has the same base (decimal) and unit (millisecond).
30
31if PHY_ADDR_ENABLE
32config PHY_ADDR
33	int "PHY address"
34	default 1 if ARCH_SUNXI
35	default 0
36	help
37	  The address of PHY on MII bus. Usually in range of 0 to 31.
38endif
39
40config B53_SWITCH
41	bool "Broadcom BCM53xx (RoboSwitch) Ethernet switch PHY support."
42	help
43	  Enable support for Broadcom BCM53xx (RoboSwitch) Ethernet switches.
44	  This currently supports BCM53125 and similar models.
45
46if B53_SWITCH
47
48config B53_CPU_PORT
49	int "CPU port"
50	default 8
51
52config B53_PHY_PORTS
53	hex "Bitmask of PHY ports"
54
55endif # B53_SWITCH
56
57config MV88E61XX_SWITCH
58	bool "Marvell MV88E61xx Ethernet switch PHY support."
59
60if MV88E61XX_SWITCH
61
62config MV88E61XX_CPU_PORT
63	int "CPU Port"
64
65config MV88E61XX_PHY_PORTS
66	hex "Bitmask of PHY Ports"
67
68config MV88E61XX_FIXED_PORTS
69	hex "Bitmask of PHYless serdes Ports"
70	default 0x0
71	help
72	  These are ports without PHYs that may be wired directly to other
73	  serdes interfaces
74
75endif # MV88E61XX_SWITCH
76
77config PHYLIB_10G
78	bool "Generic 10G PHY support"
79
80config PHY_ADIN
81	bool "Analog Devices Industrial Ethernet PHYs"
82	help
83		Add support for configuring RGMII on Analog Devices ADIN PHYs.
84
85menuconfig PHY_AQUANTIA
86	bool "Aquantia Ethernet PHYs support"
87	select PHY_GIGE
88	select PHYLIB_10G
89
90config PHY_AQUANTIA_UPLOAD_FW
91	bool "Aquantia firmware loading support"
92	depends on PHY_AQUANTIA
93	help
94		Aquantia PHYs use firmware which can be either loaded automatically
95		from storage directly attached to the phy or loaded by the boot loader
96		via MDIO commands.  The firmware is loaded from a file, specified by
97		the PHY_AQUANTIA_FW_PART and PHY_AQUANTIA_FW_NAME options.
98
99config PHY_AQUANTIA_FW_PART
100	string "Aquantia firmware partition"
101	depends on PHY_AQUANTIA_UPLOAD_FW
102	help
103		Partition containing the firmware file.
104
105config PHY_AQUANTIA_FW_NAME
106	string "Aquantia firmware filename"
107	depends on PHY_AQUANTIA_UPLOAD_FW
108	help
109		Firmware filename.
110
111config PHY_ATHEROS
112	bool "Atheros Ethernet PHYs support"
113
114config SPL_PHY_ATHEROS
115	bool "Atheros Ethernet PHYs support (SPL)"
116
117config PHY_BROADCOM
118	bool "Broadcom Ethernet PHYs support"
119
120config PHY_CORTINA
121	bool "Cortina Ethernet PHYs support"
122
123config SYS_CORTINA_NO_FW_UPLOAD
124	bool "Cortina firmware loading support"
125	depends on PHY_CORTINA
126	help
127		Cortina phy has provision to store phy firmware in attached dedicated
128		EEPROM. And boards designed with such EEPROM does not require firmware
129		upload.
130
131choice
132	prompt "Location of the Cortina firmware"
133	default SYS_CORTINA_FW_IN_NOR
134	depends on PHY_CORTINA
135
136config SYS_CORTINA_FW_IN_MMC
137	bool "Cortina firmware in MMC"
138
139config SYS_CORTINA_FW_IN_NAND
140	bool "Cortina firmware in NAND flash"
141
142config SYS_CORTINA_FW_IN_NOR
143	bool "Cortina firmware in NOR flash"
144
145config SYS_CORTINA_FW_IN_REMOTE
146	bool "Cortina firmware in remote device"
147
148config SYS_CORTINA_FW_IN_SPIFLASH
149	bool "Cortina firmware in SPI flash"
150
151endchoice
152
153config CORTINA_FW_ADDR
154	hex "Cortina Firmware Address"
155	depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
156	default 0x0
157
158config CORTINA_FW_LENGTH
159	hex "Cortina Firmware Length"
160	depends on PHY_CORTINA && !SYS_CORTINA_NO_FW_UPLOAD
161	default 0x40000
162
163config PHY_CORTINA_ACCESS
164	bool "Cortina Access Ethernet PHYs support"
165	default y
166	depends on CORTINA_NI_ENET
167	help
168		Cortina Access Ethernet PHYs init process
169
170config PHY_DAVICOM
171	bool "Davicom Ethernet PHYs support"
172
173config PHY_ET1011C
174	bool "LSI TruePHY ET1011C support"
175
176config PHY_LXT
177	bool "LXT971 Ethernet PHY support"
178
179config PHY_MARVELL
180	bool "Marvell Ethernet PHYs support"
181
182config PHY_MARVELL_10G
183	bool "Marvell Alaska 10Gbit PHYs"
184	help
185	  Support for the Marvell Alaska MV88X3310 and compatible PHYs.
186
187config PHY_MESON_GXL
188	bool "Amlogic Meson GXL Internal PHY support"
189
190config PHY_MICREL
191	bool "Micrel Ethernet PHYs support"
192	help
193	  Enable support for the GbE PHYs manufactured by Micrel (now
194	  a part of Microchip). This includes drivers for the KSZ804, KSZ8031,
195	  KSZ8051, KSZ8081, KSZ8895, KSZ886x and KSZ8721 (if "Micrel KSZ8xxx
196	  family support" is selected) and the KSZ9021 and KSZ9031 (if "Micrel
197	  KSZ90x1 family support" is selected).
198
199if PHY_MICREL
200
201config PHY_MICREL_KSZ9021
202	bool
203	select PHY_MICREL_KSZ90X1
204
205config PHY_MICREL_KSZ9031
206	bool
207	select PHY_MICREL_KSZ90X1
208
209config PHY_MICREL_KSZ90X1
210	bool "Micrel KSZ90x1 family support"
211	select PHY_GIGE
212	help
213	  Enable support for the Micrel KSZ9021 and KSZ9031 GbE PHYs. If
214	  enabled, the extended register read/write for KSZ90x1 PHYs
215	  is supported through the 'mdio' command and any RGMII signal
216	  delays configured in the device tree will be applied to the
217	  PHY during initialization.
218
219config PHY_MICREL_KSZ8XXX
220	bool "Micrel KSZ8xxx family support"
221	help
222	  Enable support for the 8000 series 10/100 PHYs manufactured by Micrel
223	  (now a part of Microchip). This includes drivers for the KSZ804,
224	  KSZ8031, KSZ8051, KSZ8081, KSZ8895, KSZ886x, and KSZ8721.
225
226endif # PHY_MICREL
227
228config PHY_MOTORCOMM
229	tristate "Motorcomm PHYs"
230	help
231	  Enables support for Motorcomm network PHYs.
232	  Currently supports the YT8511 and YT8531 Gigabit Ethernet PHYs.
233
234config PHY_MSCC
235	bool "Microsemi Corp Ethernet PHYs support"
236
237config PHY_NATSEMI
238	bool "National Semiconductor Ethernet PHYs support"
239
240config PHY_NXP_C45_TJA11XX
241	tristate "NXP C45 TJA11XX PHYs"
242	help
243	  Enable support for NXP C45 TJA11XX PHYs.
244	  Currently supports only the TJA1103 PHY.
245
246config PHY_NXP_TJA11XX
247	bool "NXP TJA11XX Ethernet PHYs support"
248	help
249	  Currently supports the NXP TJA1100 and TJA1101 PHY.
250
251config PHY_REALTEK
252	bool "Realtek Ethernet PHYs support"
253
254config RTL8211X_PHY_FORCE_MASTER
255	bool "Ethernet PHY RTL8211x: force 1000BASE-T master mode"
256	depends on PHY_REALTEK
257	help
258	  Force master mode for 1000BASE-T on RTl8211x PHYs (except for RTL8211F).
259	  This can work around link stability and data corruption issues on gigabit
260	  links which can occur in slave mode on certain PHYs, e.g. on the
261	  RTL8211C(L).
262
263	  Please note that two directly connected devices (i.e. via crossover cable)
264	  will not be able to establish a link between each other if they both force
265	  master mode. Multiple devices forcing master mode when connected by a
266	  network switch do not pose a problem as the switch configures its affected
267	  ports into slave mode.
268
269	  This option only affects gigabit links. If you must establish a direct
270	  connection between two devices which both force master mode, try forcing
271	  the link speed to 100MBit/s.
272
273	  If unsure, say N.
274
275config RTL8211F_PHY_FORCE_EEE_RXC_ON
276	bool "Ethernet PHY RTL8211F: do not stop receiving the xMII clock during LPI"
277	depends on PHY_REALTEK
278	help
279	  The IEEE 802.3az-2010 (EEE) standard provides a protocol to coordinate
280	  transitions to/from a lower power consumption level (Low Power Idle
281	  mode) based on link utilization. When no packets are being
282	  transmitted, the system goes to Low Power Idle mode to save power.
283
284	  Under particular circumstances this setting can cause issues where
285	  the PHY is unable to transmit or receive any packet when in LPI mode.
286	  The problem is caused when the PHY is configured to stop receiving
287	  the xMII clock while it is signaling LPI. For some PHYs the bit
288	  configuring this behavior is set by the Linux kernel, causing the
289	  issue in U-Boot on reboot if the PHY retains the register value.
290
291	  Default n, which means that the PHY state is not changed. To work
292	  around the issues, change this setting to y.
293
294config RTL8201F_PHY_S700_RMII_TIMINGS
295	bool "Ethernet PHY RTL8201F: adjust RMII Tx Interface timings"
296	depends on PHY_REALTEK
297	help
298	  This provides an option to configure specific timing requirements (needed
299	  for proper PHY operations) for the PHY module present on ACTION SEMI S700
300	  based cubieboard7. Exact timing requiremnets seems to be SoC specific
301	  (and it's undocumented) that comes from vendor code itself.
302
303config PHY_SMSC
304	bool  "Microchip(SMSC) Ethernet PHYs support"
305
306config PHY_TERANETICS
307	bool "Teranetics Ethernet PHYs support"
308
309config PHY_TI
310	bool "Texas Instruments Ethernet PHYs support"
311	---help---
312	  Adds PHY registration support for TI PHYs.
313
314config PHY_TI_DP83867
315	select PHY_TI
316	bool "Texas Instruments Ethernet DP83867 PHY support"
317	---help---
318	  Adds support for the TI DP83867 1Gbit PHY.
319
320config SPL_PHY_TI_DP83867
321	select PHY_TI
322	bool "Texas Instruments Ethernet DP83867 PHY support (SPL)"
323
324config PHY_TI_DP83869
325	select PHY_TI
326	bool "Texas Instruments Ethernet DP83869 PHY support"
327	---help---
328	  Adds support for the TI DP83869 1Gbit PHY.
329
330config PHY_TI_GENERIC
331	select PHY_TI
332	bool "Texas Instruments Generic Ethernet PHYs support"
333	---help---
334	  Adds support for Generic TI PHYs that don't need special handling but
335	  the PHY name is associated with a PHY ID.
336
337config PHY_VITESSE
338	bool "Vitesse Ethernet PHYs support"
339
340config PHY_XILINX
341	bool "Xilinx Ethernet PHYs support"
342
343config PHY_XILINX_GMII2RGMII
344	bool "Xilinx GMII to RGMII Ethernet PHYs support"
345	help
346	  This adds support for Xilinx GMII to RGMII IP core. This IP acts
347	  as bridge between MAC connected over GMII and external phy that
348	  is connected over RGMII interface.
349
350config PHY_XWAY
351	bool "Intel XWAY PHY support"
352	help
353	  This adds support for the Intel XWAY (formerly Lantiq) Gbe PHYs.
354
355config PHY_ETHERNET_ID
356	bool "Read ethernet PHY id"
357	depends on DM_GPIO
358	default y if ZYNQ_GEM
359	help
360	  Enable this config to read ethernet phy id from the phy node of DT
361	  and create a phy device using id.
362
363config PHY_FIXED
364	bool "Fixed-Link PHY"
365	help
366	  Fixed PHY is used for having a 'fixed-link' to another MAC with a direct
367	  connection (MII, RGMII, ...).
368	  There is nothing like autoneogation and so
369	  on, the link is always up with fixed speed and fixed duplex-setting.
370	  More information: doc/device-tree-bindings/net/fixed-link.txt
371
372config PHY_NCSI
373	bool "NC-SI based PHY"
374	depends on NET
375
376endif #PHYLIB
377
378config FSL_MEMAC
379	bool "NXP mEMAC PHY support"
380
381config SYS_MEMAC_LITTLE_ENDIAN
382	bool "mEMAC is access in little endian mode"
383	depends on FSL_MEMAC || FSL_LS_MDIO
384
385config PHY_RESET_DELAY
386	int "Extra delay after reset before MII register access"
387	default 0
388	help
389	  Some PHYs need extra delay after reset before any MII register access
390	  is possible.  For such PHY, set this option to the usec delay
391	  required.
392